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DESIGN AND IMPLEMENTATION OF SOLAR CHARGE
CONTROLLER IC USING CADENCE.
A Thesis Submitted to the Department of Electrical And Electronic Engineering in partial
Fulfillment of the Requirement for the Degree of
Bachelor of Science in Electrical and Electronic Engineering (EEE)
Department of Electrical and Electronic Engineering
United International University, Dhaka, Bangladesh
June, 2016
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A Thesis on
DESIGN AND IMPLEMENTATION OF SOLAR CHARGE
CONTROLLER IC USING CADENCE.
Submitted By-
MD. Aktarul Islam
ID: 021 121 050
Email: rahul.aktarul@gmail.com
MD. Abdur Rahim
ID: 021 121 051
Email: rahimuiu@gmail.com
Abdul Fattah
ID : 021 121 082
Email: abdu_92@yahoo.com
Sumaiya siddiquea
ID : 021 121 083
Email: sumaiyariya@gmail.com
Supervisor:
Dr. Md. Iqbal Bahar Chowdhury
Email: ibchy@eee.uiu.ac.bd
Associated Professor,
United International University
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Dedication
To our honorable Parents and faculties …………..
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Declaration
It is hereby declared that this thesis or any part of it has not been submitted elsewhere for the
award of any degree or diploma.
Signature of the Supervisor:
…………………………..…………………………………
Dr. Md. Iqbal Bahar Chowdhury
Signature of the Candidates:
……..………………………………….
Md. Aktarul Islam
…………………………………………..
Md. Abdur Rahim
…………………………………...
Abdul Fattah
…………………………………..
Sumaiya siddiquea
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Acknowledgements
The students, researchers and authors of this book are happy and delighted to
entitle the names of those who have worked hard to complete the project
entitled “DESIGN AND IMPLEMENTATION OF SOLAR CHARGE CONTROLLER
IC USING CADENCE.”.
At first, our gratitude goes to our Almighty Allah without whose blessings it is
impossible to finish the tasks we were entrusted with. We are also very much
thankful to our parents for their unconditional love, sincere advice, care and
support that have helped us to step into the step door of manhood.
Authors are greatly indebted to the supervisor of the project, Dr. Md. Iqbal
Bahar Chowdhury, Associated Professor, Dept. of EEE, UIU whose
encouragement, guidance and suggestions from the initial point to the final
phase enabled us to develop an understanding on the subject and made us
capable to complete this work successfully. Special thanks to all of our friends
for their support and encouragements. A number of ideas generated from our
numerous discussions are incorporated in this thesis.
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Abstract
Nowadays, solar charge controller plays the vital role in renewable energy
section to protect and serve the PV system. All over the world, for energy
controlling, mankind uses different solar charge controllers.
But, the price of solar charge controller is high because it generally uses
microcontrollers and PCB boards which consume energy and space.
Our main tasks were to replace the microcontrollers using analog transistors
and MOSFET’s which are measured in nanometers and consumes really low
energy and works in high frequency.
To complete the tasks, first we divided the area of charge controller system,
simulated the design and confirmed it’s working through proteus software.
Then we calculated the parameters of the controller parts and implemented in
cadence virtuoso tool.
After successful simulation, we created its Layout and connected them as the
logic system.
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CONTENT Page No.
Chapter 1
1.1 Objective
1.2 Scope
1.3 Organization
10
10
11
Chapter 2 : Overview of Solar Photovoltaic
2.1 Overview of solar PV system
2.2 Charge Transport in the Doped Silicon
2.3 Fundamental of solar cell
2.4 Effects of a P-N junction
2.5 Cell Structure
2.6 Charge transport in silicon solar cell
2.7 Theoretical Description of solar cell
2.8 Influence of Series and parallel resistance
2.9 Sources of losses in solar cell
2.10 Common Types of solar cell
11
12
13
14
16
17
17
19
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22
Chapter 3 : Overview of Solar charge controller
3.1 Charge Controller
3.2 Function of charge controller
3.3 Types of charge controller
3.4 Parallel Controller
3.5 Series Controller
3.6 Panel Charging and characteristics of controller
3.7 Charge Controller operation
3.8 Selection of Charge Controller
3.9 Voltage setting of controller
3.10MPPT Charge controller
3.11 Solar home system design with charge controller
25
26
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27
28
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29
29
30
31
Chapter 4 : Challenges of implementation of a solar charge controller in
Cadence
4.1 Switching Algorithm of solar charge controller
4.2 Step to implement the switching Algorithm of solar charge controller
4.3 Overview of working principle of Blocks of charge controller IC
4.4 Voltage compare units
4.5 Logic Units
4.6 Proteus Simulation
33
34
35
35
39
47
Chapter 5 : Cadence Implementation
5.1 About Cadence
5.2 Cadence Library
5.3 About Virtuoso tool
5.4 About Virtouso Layout Suit
5.5 Scale Calculations
48
49
49
50
51
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5.6 Analog Design Parameter
5.7 Regions of MOSFET operation
5.8 CMOS Basics
5.9 Differential Amlifier
5.10 Slew Rate
5.11 Common Source, common gate, common drain amplifier
5.12 Designing in Cadence
5.13 Comparator
5.14 Calculations
5.15 HVD
5.16 LVD
51
57
60
63
66
67
69
74
76
80
82
Chapter 6 : Conclusion 83
References 84
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CHAPTER 1
Introduction:
Solar Charge Controller components (Comparator, Microcontroller, Resistance e.t.c) are being
packaged into one single IC. Successfully simulated with Proteus initially, then implemented in
virtuoso(Schematic and Layout) using CMOS .
1.1 Objective
Solar charge controller helps to prevent batteries from overcharging. For some good quality solar
charge controllers, they helps to lengthen the effective lifespan of batteries.
A normal solar panel rated at 12V- 14V may be producing 16V to 18V at peak sun. A charge
controller helps to regulate the charging process of batteries, preventing overcharging. It also
helps to prevent electricity from flowing from the batteries to the solar panels at night.
Solar charge controller also helps to get the most out of a solar panel. This is by utilizing
MPPT(Maximum power point tracking) or PWM (Pulse Width Modulation). MPPT solar charge
controller monitors the voltage and current output of the solar panel and determines the voltage
that the panel will produce at the maximum efficiency. PWM helps to “pamper” batteries by
providing constant voltage battery charging, hence prolonging battery life. The batteries are very
expensive. It is not worth it to throw them away due to overcharging.
Hence, by doing a research and finding a good quality charge controller was our objective that
can save batteries and let a solar panel to work upto its fullest potential.
1.2 Scope
In this work, an analog model of solar charge controller has been designed. Commercially
available solar charge controller has a microcontroller which controls different voltage levels.
But these available charge controller in market places have two serious issues with cost n area.
We were assigned to replace the commercially available microcontroller based solar charge
controller by implementing the whole design on a single IC using Cadence.
The other part of assignment is to enhance the charge controller performance. A methodology
should be developed and verify so that the efficiency of the charge controller is increased
keeping the cost and area at optimum level.
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1.3 Organization
This thesis book is consisting of five chapters. The whole work is organized in the subsequent
chapters as follows. Chapter 1 describes the introduction on charge controller in general. It
provides a literature review on charge controller. Finally objective, scope of work and
organization of thesis have been provided in this chapter. In chapter two the basic overview of a
solar charge controller is described. In chapter three challenges of implementing a solar charge
controller in a IC are described. In chapter four cadence implementation, parameter calculation,
block wise design are discussed sequentially where schematic design, waveforms, layout and
DRC versus LVS are also shown. Chapter five gives the concluding remarks.
CHAPTER 2
Overview of Solar Photovoltaic
2.1 Overview
The direct transformation from the solar radiation energy into electrical energy is possible with
the photovoltaic effect by using solar cells . The term photovoltaic is often abbreviated to PV.
The radiation energy is transferred by means of the photo effect directly to the electrons in their
crystals. With the photovoltaic effect an electrical voltage develops in consequence of the
absorption of the ionizing radiation. Solar cells must be differentiated from photocells whose
conductivity changes with irradiation of sunlight. Photocells serve e.g. as exposure cells in
cameras since their electrical conductivity can drastically vary with small intensity changes.
They produce however no own electrical voltage and need therefore a battery for operation. The
photovoltaic effect was discovered in 1839 by Alexandre Edmond Becquerel while
experimenting with an electrolytic cell made up of two metal electrodes. Becquerel found that
certain materials would produce small amounts of electric current when exposed to light. About
50 years later Charles Fritts constructed the first true solar cells using junctions formed by
coating the semiconductor selenium with an ultrathin, nearly transparent layer of gold. Fritts‟s
devices were very inefficient: efficiency less than 1 %.
The first silicon solar cell with an efficiency of approx. 6% was developed in 1954 by three
American researchers, namely Daryl Chapin, Calvin Fuller and G.L. Pearson in the Bell
Laboratories. Solar cells proved particularly suitably for the energy production for satellites in
space and still represent today the exclusive energy source of all space probes. The interest in
terrestrial applications has increased since the oil crisis in 1973. Main objective of research and
development is thereby a drastic lowering of the manufacturing costs and lately also a substantial
increase of the efficiency.
The base material of almost all solar cells for applications in space and on earth is silicon. The
most common structure of a silicon solar cell is schematically represented in Figure 3-1:
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Figure 3-1: Schematic drawing of a silicon solar cell [1, 2]
An approx. 300 μm silicon wafer consists of two layers with different electrical properties
prepared by doping foreign atoms such as boron and phosphorous. The back surface side is total
metalized for charge carrier collection whereas on the front, which exposes to the beam of
incident light, only one metal grid is applied in order that as much light as possible can penetrate
into the cell. The surface is normally provided with an antireflection coating to keep the losses
from reflection as small as possible.
2.2 Charge Transport in the Doped Silicon
Now we consider the doping of silicon, a tetravalent element, which is the most frequent applied
semiconductor material, also for solar cells. Replacement of a silicon atom by a pentavalent
atom (Fig. 3-2a), e.g. phosphorus (P) or arsenic (As), leads to a surplus electron only loosely
bound by the Coulomb force, which can be ionized by an energy (ca. 0.002 eV). The quantity eV
is an energy unit corresponding to the energy gained by an electron when its potential is
increased by one volt. Since pentavalent elements donate easily an electron, one calls them
donors. The donor atom is positively charged with the electron donation (ionized). The current
transport in such a material practically occurs only by means of electrons, it is called n-type
material.
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Figure 3-2: Doping of silicon (a) with pentavalent atom (b) with trivalent atom
Replacement by a trivalent element (Fig. 3-2b), e.g. boron (B), aluminium (Al) or gallium (Ga),
leads to a lack of an electron. Now an electron in the neighborhood of a hole can fill up this
blank and leaves a new hole at its original position consequently. This results in the current
conduction by means of positive holes. Therefore this material is called p-type material.
Trivalent atoms, which easily accept an electron, are defined as acceptors. The acceptor atoms
are negatively ionized by the electron reception. At ambient temperature donors and acceptors
are already almost completely ionized in the silicon.
2.3 Fundamental of solar cell
The back surface side is total metalized for charge carrier collection where as on the front which
expose to the beam of incident light. The surface is normally provided with an antireflection
coating to keep the losses from reflection as small as possible
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2.4 Effects of a P-N Junction
Usually a p-n junction is generated by the fact that a strong n-type layer is produced in the p type
material by in diffusion of a donor (P, As) at higher temperatures (ca. 850 °C). Completely
analog in the n-type material, although less common, a p-n junction can be produced by in
diffusion of an acceptor.
In the boundary surface‟s neighborhood of the n- or p-type material the following effects occur:
In the n-region so many electrons are available, in the p-region so many holes. These
concentration differences lead to the fact that electrons from the n-region diffuse into the p
region and holes from the p-region diffuse into the n-region. As a result, diffusion currents of
electrons into the p-region and diffusion currents of holes into the n-region arise (Fig. below).
By the flow of negative and positive charges a deficit of charges develops within the before
electrically neutral regions, i.e. it results a positive charge within the donor region and a negative
charge within the acceptor region.
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Figure: Charge carrier distribution at p-n junction and currents through the junction
Thus an electrical field develops over the boundary surface and causes now field currents from
both charge carrier types, which are against the diffusion currents. In the equilibrium the total
value of current through the boundary surface is zero. The field currents compensate completely
the diffusion currents: the hole currents compensate completely among themselves and the
electron currents likewise.
This electrostatic field extending over the boundary surface refers to the potential difference VD,
which is called diffusion voltage . It is situated in the order of magnitude of 0.8 eV. This
electrical field causes the separation of the charge carriers produced by light in the solar cell.
Within the region of the stationary electrical positive and negative charge, in the so-called space-
charge zone , a lack of mobile charge carriers appears, which has very high impedance. Applying
the n-region with a negative voltage (forward bias) reduces the diffusion voltage, decreases the
electrical field strength and thus the field currents. These do not compensate now the diffusion
currents of the electrons and holes, as without external voltage, anymore. As a result a net
diffusion current from electrons and holes flows through the p-n junction. If the applied voltage
is equal to the diffusion voltage, then the field currents disappear and the current is limited only
by the bulk resistors. Contrarily, an applied positive voltage at the outside n-region (reverse bias)
adds itself to the diffusion voltage, increases the space-charge zone, thus it comes to outweighing
the field current. The resulting current whose direction of
the reverse bias is contrary is very small.
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2.5 Cell structure
Substrate Material (usually silicon)
Bulk crystalline silicon dominates the current photovoltaic market, in part due to the prominence
of silicon in the integrated circuit market.
Cell Thickness (100-500 μm)
An optimum silicon solar cell with light trapping and very good surface passivation is about 100
μm thick.
Doping of Base (1 Ω·cm)
A higher base doping leads to a higher Voc and lower resistance, but higher levels of doping
result in damage to the crystal.
Reflection Control (front surface typically textured)
The front surface is textured to increase the amount of light coupled into the cell.
Emitter Dopant (n-type)
N-type silicon has a higher surface quality than p-type silicon so it is placed at the front of the
cell where most of the light is absorbed. Thus the top of the cell is the negative terminal and the
rear of the cell is the positive terminal.
Emitter Thickness (<1μm)
A large fraction of light is absorbed close to the front surface. By making the front layer very
thin, a large fraction of the carriers generated by the incoming light are created within a diffusion
length of the p-n junction
Doping Level of Emitter (100 Ω)
The front junction is doped to a level sufficient to conduct away the generated electricity
without resistive loses. However, excessive levels of doping reduces the material's quality to the
extent that carriers recombine before reaching the junction.
Grid Pattern (fingers 20 to 200μm width, placed 1 – 5 mm apart)
The resistivity of silicon is too low to conduct away all the current generated, so a lower
resistivity metal grid is placed on the surface to conduct away the current. The metal grid shades
the cell from the incoming light so there is a compromise between light collection and resistance
of the metal grid.
Rear Contact.
The rear contact is much less important than the front contact since it is much further away from
the junction and does not need to be transparent. The design of the rear contact is becoming
increasingly important as overall efficiency increases and the cells become thinner.
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2.6 Charge transport In silicon solar cell
Effect of P-N junction
 An electrical field developed over the Boundary
surface causes field current From both charge carrier.
The mathematical process at the p-n Junction leads to
the famous diode Equation.
Where, Io= Diode current (A),
q= the electron charge
v= applied voltage
k= Boltzman constant
T = Room temperature (K)
2.7 Theoretical Description of the Solar Cell
As already mentioned, illuminated solar cell creates free charge carriers, which allow current to
flow through a connected load. The number of free charge carriers is proportional to the incident
radiation intensity. So does also the photocurrent (Iph), which is internally generated in the solar
cell. Therefore an ideal solar cell can be represented by the following simplified equivalent
circuit (Fig. below). It consists of the diode created by the p-n junction and a photocurrent source
with the magnitude of the current depending on the radiation intensity. An adjustable resistor is
connected to the solar cell as a load. The mathematical process of an ideal exposed solar cell
leads to the following equation:
Figure: Equivalent circuit diagram of an ideal solar cell connected to load
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In an imaginary experiment, the I-V characteristic curve for a certain incident radiation will now
be constructed, point for point (Fig. below):
Figure: Construction of the solar cell curve from the diode curve.
Figure: Equivalent circuit diagram of the solar cell – short-circuit current.
When the terminals are short-circuited (Rload = 0 ) (Fig. above), the output voltage and thus also
the voltage across the diode is zero. Since V = 0 , no current ID flows (point 1 in Figure 3-6)
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therefore the entire photocurrent Iph generated from the radiation flows to the output. Thus the
cell current has its maximum at this point with the value Icell and refers to the so-called short-
circuit current Isc . Isc = Icell = Iph
2.8 Influence of series- and parallel resistance
With regard to the behavior of a real solar cell, two parasitic resistances inside the cell, namely a
series- (Rs) and parallel resistance (Rp), are taken into consideration for more exact description
as indicated in the equivalent circuit diagram in Figure below.
Figure: Equivalent circuit diagram of a real solar cell
The series resistance arises from the bulk resistance of the silicon wafer, the resistance of the
metallic contacts of the front- and back surface and further circuit resistances from connections
and terminals. The parallel resistance is mainly caused by leakage currents due to p-n junction
non-idealities and impurities near the junction, which cause partial shorting of the junction,
particularly near the cell edges.
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Figure: I-V curve for different series resistances (Source: Kassel University)
Figure : I-V curve for different parallel resistances (Source: Kassel University)
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Only larger series resistances reduce also the short-circuit current whereas very small parallel
resistances reduce the open-circuit voltage. However, their influence reduces primarily the value
of the Fill factor (Fig. 3-11, Fig. 3-12). As a result, the maximum power output is decreased.
2.9 Sources of losses in solar cells
a) A part of the incident light is reflected by metal grid at the front. Additional reflection losses
arise during radiation transition from the air into the semiconductor material due to different
indexes of refraction. These losses are reduced by coating the surface with antireflection layer.
Another possibility is a structuring the cell surface.
b) The solar radiation is characterized by a wide spectral distribution, i.e. it contains photons
with extreme different energies. Photons with small energy than the band gap are not absorbed
and thus are unused. Since the energies are not sufficient to ionize electrons, electron-hole pairs
will not be
produced. In case of photons with larger energy than the band gap, only amount of energy equal
to the band gap is useful, regardless of how large the photon energy is. The excess energy is
simply dissipated as heat into the crystal lattice.
c) Since the photocurrent is directly proportional to the number of photons absorbed per unit of
time, the photocurrent increases with decreasing band gap. However, the band gap determines
also the upper limit of the diffusion voltage in the p-n junction.
A small band gap leads therefore to a small open-circuit voltage. Since the electrical power is
defined by the product of current and voltage, a very small band gaps result in small output
power, and thus low efficiencies.
In case of large band gaps, the open-circuit voltage will be high. However, only small part of the
solar spectrum will be absorbed. As a result, the photocurrent achieves here only small values.
Again, the product of current and voltage stays small.
d) The dark current I0 is larger than the theoretical value. This reduces the open-circuit voltage.
e) Not all charge carriers produced are collected, some recombine. Charge carriers recombine
preferably at imperfections, i.e. lattice defects of crystal or impurities. Therefore, source material
must have a high crystallographic quality and provide most purity.
Likewise, the surface of the semiconductor material is a place, in which the crystal structure is
very strongly disturbed, and forms a zone of increasing recombination.
f) The Fill factor is always smaller than one (theoretical max. value ca. 0.85).
g) Series- and parallel resistance result in reduction of the Fill factor [1, 2, 4].
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2.10 Common Types of Solar Cells
Hundreds of solar cells (also called photovoltaic cells) make up a solar photovoltaic (PV) array.
Solar cells are the components of solar arrays that convert radiant light from the sun into
electricity that is then used to power electrical devices and heat and cool homes and businesses.
Solar cells contain materials with semiconducting properties in which their electrons become
excited and turned into an electrical current when struck by sunlight. While there are dozens of
variations of solar cells, the two most common types are those made of crystalline silicon (both
monocrystalline and polycrystalline) and those made with what is called thin film technology.
Silicon Solar Cells
The majority of the solar cells on the market today are made of some type of silicon - by some
estimates, 90% of all solar cells are made of silicon. However, silicon can take many different
forms. Variations are most distinguished by the purity of the silicon; purity in this sense is the
way in which the silicon modules are aligned. The greater the purity of the silicon molecules, the
more efficient the solar cell is at converting sunlight into electricity. The majority of silicon
based solar cells on the market - about 95% - are comprised of crystalline silicon, making this the
most common type of solar cell. But there are two types of crystalline - monocrystalline and
polycrystalline.
Monocrystalline Silicon Solar Cells
Monocrystalline solar cells, also called "single crystalline" cells are easily
recognizable by their coloring. But what makes them most unique is that
they are considered to be made from a very pure type of silicon. In the
silicon world, the more pure the alignment
of the molecules, the more efficient the material is at converting sunlight
into electricity. In fact, monocrystalline solar cells are the most efficient
of all; efficiencies have been documented at upwards of 20%.
Monocrystalline solar cells are made out of what are called "silicon
ingots," a cylindrically shaped design that helps optimize performance.
Essentially, designers cut four sides out of cylindrical ingots to make the
silicon wafers that make up the monocrystalline panels. In this way,
panels comprised of monocrystalline cells have rounded edges rather than
being square, like other types of solar cells.
Beyond being most efficient in their output of electrical power, monocrystalline solar cells are
also the most space-efficient. This is logical since you would need fewer cells per unit of
electrical output. In this way, solar arrays made up of monocrystalline take up the least amount
of space relative to their generation intensity.
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Another advantage of monocrystalline cells is that they also last the longest of all types. Many
manufacturers offer warranties of up to 25 years on these types of PV systems.
The superiority of the monocrystalline cells comes with a price tag - in fact, solar panels made of
monocrystalline cells are the most expensive of all solar cells, so from an investment standpoint,
polycrystalline and thin film cells are often the preferred choice for consumers. One of the
reasons monocrystalline cells are so expensive is that the four sided cutting process ends up
wasting a lot of silicon, sometimes more than half.
Polycrystalline Solar Cells
Polycrystalline solar cells, also known as polysilicon and multisilicon cells, were
the first solar cells ever introduced to the industry, in 1981. Polycrystalline cells do
not go through the cutting process used for monocrystalline cells. Instead, the
silicon is melted and poured into a square mold, hence the square shape of
polycrystalline. In this way, they're much more affordable since hardly any silicon
is wasted during the manufacturing process.
However, polycrystalline is less efficient than its monocrystalline cousin.
Typically, polycrystalline solar PV system operated at a 13-16% efficiency - again,
this is due to the fact that the material has a lower purity. Due to this reality,
polycrystalline is less space-efficient, as well. One other drawback of
polycrystalline is that has a lower heat tolerance than monocrystalline, which
means they don't perform as efficiently in high temperatures.
Thin Film Solar Cells
Another up and coming type of solar cell is the thin film solar cell
with growth rates of around 60% between 2002 to 2007. By 2011,
the thin film solar cell industry represented approximately 5% of
all cells on the market.
While many variations of thin film products exist, they typically
achieve efficiencies of 7-13%. However, a lot of research and
development is being put into thin film technologies and many
scientists suspect efficiencies to climb as high as 16% in coming
models.
Thin film solar cells are characterized by the manner in which
various type of semi-conducting materials (including silicon in
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some cases) are layered on top of one another to create a series of thin films.
The major draw of thin film technologies is their cost. Mass production is much easier than
crystalline-based modules, so the cost of mass producing thin film solar cells is relatively cheap.
The product itself is also flexible in nature, which is leading to many new applications of solar
technologies in scenarios where having some type of flexible material is advantageous. Another
perk is that high heat and shading have less of a negative impact on thin film technologies. For
these reasons, the thin film market continues to grow.
One major drawback is that thin film technologies require a lot of space. This makes them less of
an ideal candidate for residential applications where space become an issue; as a result, thin film
is taking off more in the commercial space. And thin film solar cells have a shorter shelf life than
their crystalline counterparts, which is evidence by the shorter warranties offered by
manufacturers.
Thin film technology using various photovoltaic substances, including amorphous silicon,
cadmium telluride, copper indium and gallium selenide. Each type of material is suitable for
different types of solar applications.
Amorphous Silicon Solar Cells
Thin film solar cells made out of amorphous silicon are traditionally used for smaller-scale
applications, including things like pocket calculators, travel lights, and camping gear used in
remote locations. A new process called "stacking" that involves creating multiple layers of
amorphous silicon cells have resulted in higher rates of efficiency (up to 8%) for these
technologies; however, it's still fairly expensive.
Cadmium Telluride Solar Cells
Cadmium Telluride is the only of the thin-film materials that have been cost-competitive with
crystalline silicon models. In fact, in recent years, some cadmium models have surpassed them in
terms of their cost-effectiveness. Efficiency levels result in a range of 9-11%.
Copper Indium Gallium Selenide Solar Cells
Copper Indium Gallium Selenide cells have demonstrated the most promise with respect to their
efficiency levels that range from 10-12%, somewhat comparable to crystalline technologies.
However, these cells are still in the nascent stages of research and have been commercial
deployed on any wide scale. That said, the technology is most used in larger or commercial
applications.
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CHAPTER 3
Overview of Charge Controller
3.1 Charge Controller: Charge controller is an electronic device which is used in solar system.
A solar charge controller is needed in virtually all solar power systems that utilize batteries. The
job of the solar charge controller is to regulate the power going from the solar panels to the
batteries. Overcharging batteries will at the least significantly reduce battery life and at worst
damage the batteries to the point that they are unusable. The most basic charge controller simply
monitors the battery voltage and opens the circuit, stopping the charging, when the battery
voltage rises to a certain level. Older charge controllers used a mechanical relay to open or close
the circuit, stopping or starting power going to the batteries.
Modern charge controllers use pulse width modulation (PWM) to slowly lower the amount of
power applied to the batteries as the batteries get closer and closer to fully charged. This type of
controller allows the batteries to be more fully charged with less stress on the battery, extending
battery life. It can also keep batteries in a fully charged state (called―float) indefinitely. PWM is
more complex, but doesn„t have any mechanical connections to break. The electricity produced
in the solar panel is stored in the battery. The electricity stored in the battery is used at night.
This whole process is monitored by the charge controller. A typical charge controller (Phocos) is
shown in the figure bellow
Figure: Charge controller
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3.2 Function of charge controller
The main function of a charge controller or
regulator is to fully charge a battery without permitting overcharge while preventing
reverse current flow at night. Other functions are-
Stop the process of the battery when it is fully charged.
Disconnect the load during low voltage.
Disconnect the load during high voltage.
Monitor the battery voltage, state of charge, SOC etc.
To give alarm during fault condition.
Current measurement.
Detect when no energy is coming from the solar panels and open the circuit,
disconnecting the solar panels from the batteries and stopping reverse current flow.
Charge controller is used for co-ordination and control among the battery, load and solar panel.
Charge controller stores the electricity in the battery during day time and supplies the same to the
load (mainly lamp) at night. On the other hand, if battery is fully charged, then charge controller
can directly supply electricity to the load (Fan, mobile charger etc) from the solar panel during
day time. A charge controller or charge regulator is mainly worked as a voltage regulator.
Generally it controls the voltage and current of the solar panel to save in battery. Solar panel
mainly produces 16 volts to 21 volt and 14 volt to 14.4 volt is required to keep the battery in full
charged state. The charge controller works as a Buck converter to minimize this voltage level.
Charge controller is mainly a Chopper or DC-DC converter. Buck converter is usually used in
the solar panel which converts the
high level DC voltage to the low level DC voltage.
3.3 Types of Charge controller
Charge controller connection mainly two types-
1. Parallel or shunt controller
2. Series controller
3.4 Parallel Controller:
Figure: Use of Shunt controller in solar home system
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In this system, charge controller is in parallel with the battery and load. When the battery is fully
charged, then the solar panel is short circuited by the controller In this system, a ―Blocking
diode is needed. So that reverse current would not flow from battery to thepanel. When the
battery is charged through this blocking diode, it gets hot.
Disadvantages of shunt controller:
 Lose of electricity
 When the panel is short circuited, huge amount of short circuit current flows
through the switch (FET).
 Shunt controller gets hotter compared to series controller.
 There is a chance of hot spot on the panel.
3.5 Series Controller:
Figure: Use of Shunt controller in solar home system
In this system, charge controller is connected in between with the solar panel and battery. In
order to terminate the flow of electricity to the battery, the series controller must be removed
from the battery. There‟s no need of blocking diode in this system, but in many reasons it is used
to terminate the process of discharging at night. The resistance should be maintained as low as
possible in order to minimize lose of the electricity.
Advantages of series controller:
Blocking diode is not required.
Series controller switch is handled with low voltage compared to shunt controller.
Low switching noise.
It is possible of precision charge and PWM of the battery.
No chance of hot spot like the shunt controller .
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3.6 Panel charging and characteristics of controller:Below figure shows how different kinds
of charge controller controls the voltage andcurrent. The upper curve shows the battery voltage
and the lower curve shows panel current. a,b,c,d indicates controller„s action .
Below figure shows how different kinds of charge controller controls the voltage and current.
The upper curve shows the battery voltage and the lower curve shows panel current. a,b,c,d
indicates controller„s action .
Figure: Relation between different types of charge controller and battery
voltage and current
3.7 Charge Controller Operation: Fixed Set Point:
To terminate the panel current when it reaches to the maximum voltage level and then continue it
again when it reaches to the minimum voltage level is called ―Set point. The relation between
charging-discharging of a battery and voltage is shown in the figure bellow-
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Figure: Set point of controller (Micro-controller based)
There„s a possibility of the damage of the battery (50-100%) if the voltage level is set as the red
dotted line of the above figure. We can match the controller„s voltage-current with the state of
charge (SOC) by using micro-controller and Fuzz logic. This will reduce the probability of
damaging the battery (10-20%).
3.8 Selection of charge controller
Solid state series controller is suitable for small system (4 ampere). Solid state shunt controller is
suitable for the system of 4 to 30 ampere.
A good controller must have following features-
Low voltage disconnection
Battery charging current indicator (LED or meter).
Battery voltage indicator (LED or meter).
Sense lead.
Adjustable set point.
Ability of Communication (for large system).
Data logger
Computer interface
3.9 Voltage setting of controller
The following factors are responsible for the voltage setting of controller-
Types of battery
Charging characteristics of charge controller
Size of the battery
Maximum panel current
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Figure: A solid state series controller and its various parts
3.10 MPPT Charge controller
MPPT charge controller is a maximum power point tracker which is an electronic DC to DC
converter which takes the DC input from the solar panels, changes it to high frequency AC and
converts it back to a different DC current to match with the batteries. This is a solely electronic
tracking system and not concerned with the panel system at all.
Figure: Phocos MPPT 100/20(20 amps)
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3.11 Solar home system design with charge controller
The basic components are PV module, Charge controller, Battery, Inverter, Wire. For calculation
first we need to know our demand and running hour. Think our demand is 200 W and duration of
running hour is 4 hour. So 200* 4=800Wh.The formula of PV design is
PV module = demand watt hours* de-rating factor /peak sun.
Suppose peak sun is 4.5 hour de-rating factor is 1.3. So PV module =800*1.3/4.5 =231.111W.
So we need three 85 Wp module which give 255W.The formula of PV calculation is Capacity of
charge controller= demand watt *safety factor/system voltage=
200*1.25/12=20.83333A/12V.This result is fraction so we use 25A/12V charge controller. The
formula of battery sizing is Battery capacity= demand Wh* Autonomy/efficiency*DOD*System
voltage. Here DOD is depth of discharge and autonomy is number of day we use battery as
abackup power. Suppose DOD is .6 and autonomy is 1 day, efficiency is 8.
So, battery capacity =800*1/.8*.6*12 =138.888Ah.The calculation for inverter is
Inverter = demand *safety factor=200*1.25 =250 W 220V Ac /12 V DC.
Fig : Connecting diagram for dc current
Fig: connecting diagram for ac
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CHAPTER 4
Challenges of implementation of solar charge controller in cadence
In this chapter, we discuss about the challenges of implementing and design of a solar charge
controller in Analog IC.
A charge controller is required in most PV systems that use battery storage to regulate battery
state-of-charge, optimize battery and system performance, and help prevent damage to the
batteries or hazardous conditions resulting from the charging process.
Figure: Simple block diagram of Charge controller.
Functions of charge controllers include:
 Battery overcharge and/or over discharge protection
 Control of loads or other energy sources
Features of charge controllers include:
 Type of switching and control algorithm
 Equalization charging
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Figure: Two main work of charge controller.
4.1 Switching Algorithm of solar charge controller
Figure: Circuit block diagram of charge controller.
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This block diagram shows the main switching function of charge controller. Switch1 control the
battery charging condition and switch 2 control the load condition. These two switches operate
based on battery voltages that we concern i.e. 14.4v,13.8v,12.6v and 10.8v. These voltages based
operation are shown in below table.
Voltage
value
Switch 1
status
Switch 2
status
Priority Condition
HVD >14.4 OFF D PV disconnected from the Battery.
HVR <13.8 ON D PV connected to Battery.
LVD <10.8 D OFF Battery disconnected from the load.
LVR >12.6 D ON Battery connected to load.
In this table, we can see that we consider four battery voltages point i.e.
 HVD (High voltage disconnect)
 HVR (High voltage re-connect)
 LVD (Low voltage disconnect)
 LVR (Low voltage re-connect)
Mainly High voltages conditions is mainly used for sensing the charging condition and low
voltages points are being concerned about loading condition. For this reason and simplify our
design we used don‟t care condition, which is denoted by D.
4.2 Step to implement the Switching Algorithm of solar charge controller.
Our main challenges are replacing the switching circuits with analog IC. To do this, we have to
understand the main working principle of charge controller. What a charge controller mainly do?
Charge controller mainly follow some step i.e.
 Take input voltage from battery.
 Compare voltage.
 Execution of logic.
 Take decision.
 Execute Instruction.
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So, to design a solar charge IC, we have to follow the step. But we complete this step, we design
and implement some block units and attach them in the last step.
4.3 Overview of working principle of Blocks of charge controller IC.
Figure: Blocks of solar controller.
We can see that there are four block units. i.e
 Input
 Voltage compare
 Logic units or decision taking unit.
 Execution unit or Output.
Input and Output units are mainly very simple design. Here we use some voltage divider and
deriver MOS to drive the load. To implement the block, we have to concern about the voltage
compare units which compare the battery voltage and Logic units which take the controlling
decision.
4.4 Voltage compare Units
In this units, we compare the battery voltage with our ref. voltage.
Use 4 voltage comparator to compare four battery voltage points (14.4v,13.8v,12.6v and
10.8v). After compare gives output value either VDD or GND.
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Voltage comparator:
A dedicated voltage comparator will generally be faster than a general-purpose operational
amplifier pressed into service as a comparator. A dedicated voltage comparator may also contain
additional features such as an accurate, internal voltage reference, an adjustable hysteresis and a
clock gated input.
A dedicated voltage comparator chips such as LM339 is designed to interface with a digital logic
interface (to a TTL or a CMOS). The output is a binary state often used to interface real world
signals to digital circuitry. If there is a fixed voltage source from, for example, a DC adjustable
device in the signal path, a comparator is just the equivalent of a cascade of amplifiers. When the
voltages are nearly equal, the output voltage will not fall into one of the logic levels, thus analog
signals will enter the digital domain with unpredictable results. To make this range as small as
possible, the amplifier cascade is high gain. The circuit consists of mainly Bipolar transistors.
For very high frequencies, the input impedance of the stages is low. This reduces the saturation
of the slow, large P-N junction bipolar transistors that would otherwise lead to long recovery
times. Fast small Schottky diodes, like those found in binary logic designs, improve the
performance significantly though the performance still lags that of circuits with amplifiers using
analog signals. Slew rate has no meaning for these devices. For applications in flash ADCs the
distributed signal across eight ports matches the voltage and current gain after each amplifier,
and resistors then behave as level-shifters.
The LM339 accomplishes this with an open collector output. When the inverting input is at a
higher voltage than the non-inverting input, the output of the comparator connects to the negative
power supply. When the non-inverting input is higher than the inverting input, the output is
'floating' (has a very high impedance to ground). The gain of op amp as comparator is given by
this equation V(out)=V(in)
How to Use an Op Amp as a Voltage Comparator?
A voltage comparator is an electronic circuit that compares two input voltages and lets you
know which of the two is greater. It‟s easy to create a voltage comparator from an op amp,
because the polarity of the op-amp‟s output circuit depends on the polarity of the difference
between the two input voltages.
Suppose that you have a photocell that generates 0.5 V when it‟s exposed to full sunlight, and
you want to use this photocell as a sensor to determine when it‟s daylight. You can use a voltage
comparator to compare the voltage from the photocell with a 0.5 V reference voltage to
determine whether or not the sun is shining.
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In the voltage-comparator circuit, first a reference voltage is applied to the inverting input (V–);
then the voltage to be compared with the reference voltage is applied to the noninverting input.
The output voltage depends on the value of the input voltage relative to the reference voltage, as
follows:
Input Voltage Output Voltage
Less than reference voltage Negative
Equal to reference voltage Zero
Greater than reference voltage Positive
Note that the voltage level for both the positive and negative output voltages will be about 1 V
less than the power supply. Thus, if the op-amp power supply is 9 V, the output voltage will be
+8 V if the input voltage is greater than the reference voltage, 0 V if the input voltage is equal to
the reference voltage, and –8 V if the input voltage is less than the reference voltage.
You can modify the circuit to eliminate the negative voltage if the input is less than the reference
by sending the output through a diode. In this circuit, a positive voltage appears at the output if
the input voltage is greater than the reference voltage; otherwise, no output voltage exists.
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To create a voltage comparator that creates a positive voltage output if the input voltage is less
than a reference voltage, apply the reference voltage to the inverting (V–) input, and the input
voltage is applied to the noninverting (V+) input.
The final voltage-comparator circuit you should know about is the window comparator, which
lets you know whether the input voltage falls within a given range. A window comparator
requires three inputs: a low reference voltage, a high reference voltage, and an input voltage.
The output of the window comparator will be a positive voltage only if the input voltage is
greater than the low reference voltage and less than the high reference voltage. If the input
voltage is less than the low reference voltage, the output will be zero. Similarly, if the input
voltage is greater than the high reference voltage, the output will also be zero.
You need two op amps to create a window comparator. One op amp is configured to produce
positive output voltage only if the input is greater than the low reference voltage (VREF(LOW)).
The other op amp is configured to produce positive output voltage only if the input is less than
the high reference voltage (VREF(HIGH)).
The input voltage is connected to both op amps; the output voltage is sent through diodes to
allow only positive voltage and then combined. The resulting output will have positive voltage
only if the input voltage falls between the low and high reference voltages.
In this unit, we design an op-amp based voltage comparator. We discuss the design and it‟s
calculation in the next chapter.
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4.5 Logic Units
The logic unit, which take the input as digital value i.e. 5/0 from the comparator output,
take the decision for charging condition and load control condition and finally, give a
digital output which is our main output pin. Observing the voltage comparator output and
considering our switching diagram we two same but separate logic for charging condition
and load controlling condition. The schematic of logic circuits is given bellow:
Figure: Logic circuit
40 | P a g e
 Two Logic units for switch 1 and switch 2.
 Logic circuits consist of an AND gate and OR gate.
Now, we discuss the working principle of AND gate and OR gate.
AND-Gate:
A Logic AND Gate is a type of digital logic gate that has an output which is normally at logic
level “0” and only goes “HIGH” to a logic level “1” when ALL of its inputs are at logic level
“1”. The output state of a “Logic AND Gate” only returns “LOW” again when ANY of its inputs
are at a logic level “0”. In other words, for a logic AND gate, any LOW input will give a LOW
output.
The logic or Boolean expression given for a digital logic AND gate is that for Logical
Multiplication which is denoted by a single dot or full stop symbol, ( . ) giving us the Boolean
expression of: A.B = Q.
Then we can define the operation of a 2-input logic AND gate as being:
“If both A and B are true, then Q is true”
2-input Transistor AND Gate
A simple 2-input logic AND gate can be constructed using RTL Resistor-transistor switches
connected together as shown below with the inputs connected directly to the transistor bases.
Both transistors must be saturated “ON” for an output at Q.
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Logic AND Gates are available using digital circuits to produce the desired logical function and
is given a symbol whose shape represents the logical operation of the ANDgate.
Digital Logic “AND” Gate Types
The 2-input Logic AND Gate
Symbol Truth Table
2-input AND Gate
B A Q
0 0 0
0 1 0
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1 0 0
1 1 1
Boolean Expression Q = A.B Read as A AND B gives Q
The 3-input Logic AND Gate
Symbol Truth Table
3-input AND Gate
C B A Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
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1 0 1 0
1 1 0 0
1 1 1 1
Boolean Expression Q = A.B.C Read as A AND B AND C gives Q
Because the Boolean expression for the logic AND function is defined as (.), which is a binary
operation, AND gates can be cascaded together to form any number of individual inputs.
However, commercial available AND gate IC‟s are only available in standard 2, 3, or 4-input
packages. If additional inputs are required, then standard AND gates will need to be cascaded
together to obtain the required input value, for example.
Multi-input AND Gate
The Boolean Expression for this 6-input AND gate will therefore be: Q = (A.B).(C.D).(E.F)
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OR-GATE:
A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an output which is
normally at logic level “0” and only goes “HIGH” to a logic level “1” when one or more of its
inputs are at logic level “1”. The output, Q of a “Logic OR Gate” only returns “LOW” again
when ALL of its inputs are at a logic level “0”. In other words, for a logic OR gate, any “HIGH”
input will give a “HIGH”, logic level “1” output.
The logic or Boolean expression given for a digital logic OR gate is that for Logical
Addition which is denoted by a plus sign, ( + ) giving us the Boolean expression of: A+B = Q.
Then we can define the operation of a 2-input logic OR gate as being:
“If either A or B is true, then Q is true”
2-input Transistor OR Gate
A simple 2-input logic OR gate can be constructed using RTL Resistor-transistor switches
connected together as shown below with the inputs connected directly to the transistor bases.
Either transistor must be saturated “ON” for an output at Q.
45 | P a g e
desired logical function and is given a symbol whose shape represents the logical operation of
the OR gate.
Digital Logic “OR” Gate Types
The 2-input Logic OR Gate
Symbol Truth Table
2-input OR Gate
B A Q
0 0 0
0 1 1
1 0 1
1 1 1
Boolean Expression Q = A+B Read as A OR B gives Q
The 3-input Logic OR Gate
Symbol Truth Table
3-input OR Gate
C B A Q
0 0 0 0
0 0 1 1
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0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Boolean Expression Q = A+B+C Read as A OR B OR C gives Q
Like the AND gate, the OR function can have any number of individual inputs. However,
commercial available OR gates are available in 2, 3, or 4 inputs types. Additional inputs will
require gates to be cascaded together for example.
Multi-input OR Gate
The Boolean Expression for this 6-input OR gate will therefore be: Q = (A+B)+(C+D)+(E+F)
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If the number of inputs required is an odd number of inputs any “unused” inputs can be held
LOW by connecting them directly to ground using suitable “Pull-down” resistors.
4.6 Proteus Simulation
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Chapter 5
Cadence Implementations
5.1 About Cadence:
Today Electronics devices are everywhere, in pockets, cars, homes, workplaces,
everywhere. Smartphonees and mobile devices connect everyone, anywhere. These
mobiles contain ‘apps’ which complete different complex tasks for the users.
This newly connected, ‘app dependent’ world is built on the revolution of semiconductor
and manufacturing. A single device might be built on billions of transistors. Systems-on-
chips(SoCs) combine processors, memory, analog components, interface protocols and
more. These type of complex calculations need huge powerful software for design,
while meeting demands for performance, low power, and time to market. EDA
(Electronic Design Automation) tools make it possible. EDA software and hardware
enables everything from the design of individual transistors to the development of
software before any hardware is built. Also, semiconductor intellectual property (IP)
which provides pre-verified building blocks for memory controllers, specialized
processors that are integrated into SoCs.
Cadence is the leading provider of EDA and Semiconductor IP.
Products of Cadence:
Cadence's product offerings are targeted at various types of design and verification
tasks which include:
 Virtuoso Platform - Tools for designing full-custom integrated circuits, includes
schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom
layout, physical verification, extraction and back-annotation. Used mainly for analog,
mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.
 Encounter Platform - Tools for implementation of digital integrated circuits. This
includes floorplanning, test, place and route and clock tree synthesis. Typically a
digital design implementation starts from Verilog netlists from the synthesized
design. Includes Nanoroute technology in the routing stage.
 Incisive Platform - Tools for simulation and functional
verification of RTL including Verilog, VHDL and SystemC based models.
Includes formal verification, formal equivalence checking, hardware acceleration,
and emulation.
 Palladium series - Accelerators and emulators for hardware and software co-
verification and system-level verification.
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 Design IP - Cadence provides design IP targeting areas including memory (DRAM),
covering DDR1, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and Wide I/O;
storage (non-volatile memory), covering NVM Express and NAND Flash controller
and PHY; and high-performance interface protocols such as PCI Express Gen3,
40/100G Ethernet, and USB 2 and USB 3.
 Verification IP (VIP) - Cadence provides the broadest set of commercial VIP
available with over 30 protocols in its VIP Portfolio. They include AMBA, PCI
Express, USB, SATA,OCP, SAS, MIPI and many others. Cadence VIP also provides
the unique Compliance Management System (CMS) to automate protocol
compliance verification.
 Integration Optimized IP (Design IP) - Cadence offers Vertically Integrated IP,
inclusive of Digital Controller, Serdes Layer, and Device Driver. Protocols supported
include USB, DDR, PCI-Express, 10G-40G Ethernet, and On Chip Bus Fabric.
 Allegro Platform - Tools for co-design of integrated circuits, packages, and PCBs.
 OrCAD/PSpice - Tools for smaller design teams and individual PCB designers.[14]
 Sigrity technologies - Tools for signal and power verification for system-level
signoff verification and interface compliance.[15]
 Since the acquisition of Tensilica in 2013 in the business of semiconductor
intellectual property core
In addition to EDA software, Cadence provides contracted methodology and design
services as well as silicon design IP, and has a program aimed at making it easier for
other EDA software to interoperate with the company's tools.
5.2 Cadence Library:
Generic Process Design Kit(GPDK) known as cadence library. There are 45nm
Process, 90nm Process, 180nm Process etc.
5.3 About Virtouso tool:
Virtuoso creates Analog Design Environment for advanced design and simulation. It
gives access to a new parasitic estimation and comparison flow and optimization
algorithms that help to center designs better for yield improvement and advanced
matching and sensitivity analyses. By supporting extensive exploration of multiple
designs against their objective specifications, Virtuoso Analog Design Environment sets
the standard in fast and accurate design verification.
Features/Benefits
Reduced learning curve with a simulator-independent environment
Maximum efficiency in the script-driven mode
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Accelerated debug process using a variety of built-in analog analysis tools
Facilitated design correction via easy comparison of pre- and post-parasitic extracted
designs
Quick detection of circuit problems via a clear visualization cockpit.
5.4 About Virtuoso Layout Suite:
Cadence Virtuoso Layout Suite supports custom analog, digital, and mixed-signal
designs at the device, cell, block, and chip levels. The enhanced Virtuoso Layout Suite
offers accelerated performance and productivity from advanced full custom polygon
editing through more flexible schematic and constraint-driven full custom layout, to full
custom layout automation. Seamlessly integrated with the Virtuoso Schematic Editor
and the Virtuoso Analog Design Environment, the Virtuoso Layout Suite enables the
creation of differentiated custom silicon that is both fast and silicon accurate.
Features/Benefits
 New patented graphics-rendering engine provides from 10X to 100X accelerated zoom,
fit, pan, drag, and redraw performance on large layouts
 New Virtuoso Layout Suite XL connectivity extractor technology accelerates trace net,
probe net, and mark net performance from 10X to 50X on large layouts
 Patented multi-user Express PCell capability continues to boost design opening
performance from 10X to 20X whenever users require PCell evaluation
 New patented stream in engine provides accelerated performance from 2X to 20X
 Virtuoso Space-Based Routing technology automatically enforces process and design
rules during interactive and assisted wire and bus editing
 Virtuoso module generators (ModGens) add a new interactive pattern manipulation flow,
making real-time customization of a high-precision structured layout very visual and
simple
 Virtuoso Space-Based Routing technology at chip levels can deliver high-quality
constraints and specialty routing to close thousands of nets in minutes, and new
structured device-level routing capabilities that can enhance routing productivity by as
much as 50%
 The Virtuoso platform is backed by the largest number of process design kits (PDKs)
available from the world’s leading foundries, for process nodes everywhere from mature
0.6µm to advanced 7nm process node.
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5.5 Scale-Calculations:
Scale calculation refers to the number of transistors/MOSFETS in a design. Typical
scale division are:
Scale No of transistors
small-scale integration (SSI) 2-100
medium-scale integration (MSI) 100–500
large-scale integration (LSI) 500–20,000
very-large-scale integration (VLSI) 20,000–1,000,000
ultra-large scale integration (ULSI) >1,000,000
5.6 Analog Design Parameters:
5.6.1 The MOSFET
The MOSFET – Metal Oxide FET
Or, Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor
available whose Gate input is electrically insulated from the main current carrying channel and is
therefore called an Insulated Gate Field Effect Transistor or IGFET.
The most common type of insulated gate FET which is used in many different types of electronic
circuits is called the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for
short
The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET
in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main
semiconductor n-channel or p-channel by a very thin layer of insulating material usually silicon
dioxide, commonly known as glass.
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This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor. The
isolation of the controlling Gate makes the input resistance of the MOSFET extremely high way
up in the Mega-ohms ( MΩ ) region thereby making it almost infinite.
As the Gate terminal is isolated from the main current carrying channel “NO current flows into
the gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the
current flowing through the main channel between the Drain and Source is proportional to the
input voltage. Also like the JFET, the MOSFETs very high input resistance can easily
accumulate large amounts of static charge resulting in the MOSFET becoming easily damaged
unless carefully handled or protected.
MOSFETs are three terminal devices with a Gate, Drain and Source and both P-channel (PMOS)
and N-channel (NMOS) MOSFETs are available. The main difference this time is that
MOSFETs are available in two basic forms:
 Depletion Type – the transistor requires the Gate-Source voltage, (VGS ) to switch the
device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch.
 Enhancement Type – the transistor requires a Gate-Source voltage, (VGS ) to switch the
device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open”
switch.
The symbols and basic construction for both configurations of MOSFETs are shown below
MOSFET
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The four MOSFET symbols above show an additional terminal called the Substrate and is not
normally used as either an input or an output connection but instead it is used for grounding the
substrate. It connects to the main semi conductive channel through a diode junction to the body
or metal tab of the MOSFET. Usually in discrete type MOSFETs, this substrate lead is connected
internally to the source terminal. When this is the case, as in enhancement type it is omitted from
the symbol for clarification.
The line between the drain and source connections represents the semi conductive channel. If
this is a solid unbroken line then this represents a “Depletion” (normally-ON) type MOSFET as
drain current can flow with zero gate potential. If the channel line is shown dotted or broken it is
an “Enhancement” (normally-OFF) type MOSFET as zero drain current flows with zero gate
potential. The direction of the arrow indicates whether the conductive channel is a p-type or an
n-type semiconductor device.
Basic MOSFET Structure and Symbol
The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction
FET. Both the Depletion and Enhancement type MOSFETs use an electrical field produced by a
gate voltage to alter the flow of charge carriers, electrons for n-channel or holes for P-channel,
through the semi conductive drain-source channel. The gate electrode is placed on top of a very
thin insulating layer and there are a pair of small n-type regions just under the drain and source
electrodes.
The gate of a junction field effect transistor, JFET must be biased in such a way as to reverse-
bias the pn-junction. With a insulated gate MOSFET device no such limitations apply so it is
possible to bias the gate of a MOSFET in either polarity, positive (+ve) or negative (-ve).
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This makes the MOSFET device especially valuable as electronic switches or to make logic
gates because with no bias they are normally non-conducting and this high gate input resistance
means that very little or no control current is needed as MOSFETs are voltage controlled
devices. Both the p-channel and the n-channel MOSFETs are available in two basic forms,
the Enhancement type and the Depletion type.
Depletion-mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement mode types is
normally switched “ON” (conducting) without the application of a gate bias voltage. That is the
channel conducts when VGS = 0 making it a “normally-closed” device. The circuit symbol shown
above for a depletion MOS transistor uses a solid channel line to signify a normally closed
conductive channel.
For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will deplete
(hence its name) the conductive channel of its free electrons switching the transistor “OFF”.
Likewise for a p-channel depletion MOS transistor a positive gate-source voltage, +VGS will
deplete the channel of its free holes turning it “OFF”.
In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and
more current. While a -VGS means less electrons and less current. The opposite is also true for
the p-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed”
switch.
Depletion-mode N-Channel MOSFET and circuit Symbols
55 | P a g e
The depletion-mode MOSFET is constructed in a similar way to their JFET transistor
counterparts were the drain-source channel is inherently conductive with the electrons and holes
already present within the n-type or p-type channel. This doping of the channel produces a
conducting path of low resistance between the Drain and Source with zero Gate bias.
Enhancement-mode MOSFET
The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the
depletion-mode type. Here the conducting channel is lightly doped or even undoped making it
non-conductive. This results in the device being normally “OFF” (non-conducting) when the
gate bias voltage, VGS is equal to zero. The circuit symbol shown above for an enhancement
MOS transistor uses a broken channel line to signify a normally open non-conducting channel.
For the n-channel enhancement MOS transistor a drain current will only flow when a gate
voltage (VGS ) is applied to the gate terminal greater than the threshold voltage ( VTH ) level in
which conductance takes place making it a trans conductance device.
The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons
towards the oxide layer around the gate thereby increasing or enhancing (hence its name) the
thickness of the channel allowing more current to flow. This is why this kind of transistor is
called an enhancement mode device as the application of a gate voltage enhances the channel.
Increasing this positive gate voltage will cause the channel resistance to decrease further causing
an increase in the drain current, ID through the channel. In other words, for an n-channel
enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS turns the
transistor “OFF”. Then, the enhancement-mode MOSFET is equivalent to a “normally-open”
switch.
The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device is
“OFF” and the channel is open. The application of a negative (-ve) gate voltage to the p-type
eMOSFET enhances the channels conductivity turning it “ON”. Then for an p-channel
enhancement mode MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the transistor
“ON”.
56 | P a g e
Enhancement-mode N-Channel MOSFET and Circuit Symbols
Enhancement- mode
MOSFETs make excellent electronics
switches due to their low “ON” resistance
and extremely high “OFF” resistance as
well as their infinitely high input
resistance due to their isolated gate. Enhancement-mode MOSFETs are used in integrated
circuits to produce CMOS type Logic Gates and power switching circuits in the form of as
PMOS (P-channel) and NMOS (N-channel) gates. CMOS actually stands for Complementary
MOS meaning that the logic device has both PMOS and NMOS within its design.
So, the summary of MOSFET can be showed by this chart:
57 | P a g e
5.6.2 Why use MOSFET over BJT as a switch?
MOSFET BJT
Voltage Driven Current Driven
Works in High and low frequencies Works in lower frequencies than MOSFET
Swithes faster Swithes lower than MOSFET
Wastes no current on gate Wastes current on base
More energy efficient Less energy efficient
Suitable for driving high power Suitable for driving low powr
More expensive Less expensive
If both of the characteristics are needed somewhere, we can use IGBT (insulated-gate
bipolar transistor )
IGBT comparison table:
5.7 Regions of MOSFET operation:
58 | P a g e
VGS = voltage between gate to source
VDS = voltage between drain to source
ID = current flowing through drain.
VT = Threshold voltage(Minimum voltage to switch ON a MOSFET)
If we give a gate voltage to MOSFET gate, according to the voltage, the MOSFET switches.
MOSFET Regions of Operation
• There are three regions of operation in the MOSFET
– When VGS < VT, no conductive channel is present and ID = 0, the cutoff region
– When VGS < VT and VDS < VDS, sat, the device is in the triode region of operation.
Increasing VDS increases the lateral field in the channel, and hence the current. Increasing VGS
increases the transverse field and hence the inversion layer density, which also increases the
current
– If VGS < VT and VDS > VDS, sat, the device is in the saturation region of operation. Since the
drain end channel density has become small, the current is much less dependent on VDS , but is
still dependent on VGS, since increased VGS still increases the inversion layer density
MOSFET ID-VDS Characteristic
For VGS < VT , ID = 0 .
As VDS increases at a fixed VGS , ID increases in the triode region
due to the increased lateral field, but at a decreasing rate since the
inversion layer density is decreasing.
Once pinchoff is reached, further VDS increases only increase ID
due to the formation of the high field region.
MOSFET ID-VGS Characteristic
As ID is increased at fixed VDS, no current flows until the inversion layer is established.
For VGS slightly above threshold, the device is in saturation since there is little inversion layer
density (the drain end is pinched off)
As VGS increases, a point is reached where the drain end is no longer pinched off, and the
device is in the triode region.
A larger VDS value postpones the point of transition to triode.
59 | P a g e
The device starts in triode, and moves into saturation at higher VDS.
MOSFET equations:
60 | P a g e
5.8 CMOS Basics:
Complementary CMOS
 Comlementary CMOS Logic Gates:
 nMOS pull-down network „
 pMOS pull-up network „
 Static CMOS
61 | P a g e
 Complementary CMOS gates always produce 1 or 0
 Pull-up network is complement (dual) of pull-down network
Building CMOS Gates (n-side)
CMOS is inherently inverting. „
 Gates with expression of the form F = 𝐸𝑋𝑃𝑅𝐸𝑆𝑆𝐼𝑂𝑁 are easier to build.
 For making the n-side (pull-down network) use the un-inverted expression.
 For e.g.: Implement „F = ( 𝐴. 𝐵 + 𝐶. 𝐷 )
 For n-side use „F= ((A.B)+(C.D))
 AND expressions are implemented using series connection of n transistors „
 OR expressions are implemented using parallel connection of n transistors.
Building CMOS Gates (p-side)
 For making the p-side (pull-up network) invert the expression used for n-side. „
 For e.g.: Implement „F = ( 𝐴. 𝐵 + 𝐶. 𝐷 )
 For n-side use F= ((A.B)+(C.D))
 For p-side invert above expression: „F = (𝐴 + 𝐵).(𝐶 + 𝐷)
 AND expressions are implemented using series connection of p transistors „
 OR expressions are implemented using parallel connection of p transistors
62 | P a g e
Building CMOS Gates (Final CMOS gate)
Combine the n-side (pull-down) and p-side (pull-up) to make the final gate.
F = ( 𝐴. 𝐵 + 𝐶. 𝐷 )
63 | P a g e
5.9 Differential Amplifier
MOSFET is the most widely used transistor in both digital and analog circuits, and it is the
backbone of modern electronics. One of the most common uses of the MOSFET in analog
circuits is the construction of differential amplifiers. The latter are used as input stages in op-
amps, video amplifiers, high-speed comparators, and many other analog-based circuits.
MOSFET differential amplifiers are used in integrated circuits, such as operational amplifiers,
they provide high input impedance for the input terminals. A properly designed differential
amplifier with its current-mirror biasing stages is made from matched-pair devices to minimize
imbalances from one side of the differential amplifier to the other.
Differential Amplifier: An electronic amplifier amplifies the difference between two
input voltages but suppresses any voltage common to the two inputs. It is an analog
circuit with two inputs Vin+ and Vin- and one output Vout in which the output is ideally
proportional to the difference between the two voltages.
Vout = A(Vin+ - Vin-)
where A is the gain of the amplifier.
In the figure , V+ = Vin+
V- = Vin-
BACKGROUND :
The general topology of a differential amplifier is shown below. Two active devices are
connected to a positive voltage supply via passive series elements. The transistors must be a
matched pair (i.e., two matched MOSFETs or two matched BJTs). The "pull up" loads are
similarly matched to each other. The lower terminals of the active devices are connected
together, and a dc current source pulls current down toward the negative voltage bus to effect
the bias. The controlling input ports of the devices are connected to input signals.
64 | P a g e
If the input signals are designated v1 and v2 , they can be decomposed into two linear
combinations, one called the differential mode, and the other the common mode. The
differential mode is defined by the following equation:
vidm = v1-v2
Similarly, the common mode, equal to the average value of the signals, is defined by:
vicm =
v1+v2
2
These definitions allow the actual input signals v1 and v2 to be expressed as linear
combinations of their differential and common modes:
v1 = vicm +
vidm
2
=
v1+v2
2
+
v1−v2
2
= v1
v2 = vicm -
vidm
2
=
v1+v2
2
-
v1−v2
2
= v2
because the small-signal model of the amplifier is linear, its total response will be equal to the
superposition of its responses to, respectively, the differential and common modes of the input
signals.
Current Mirror MOFETS:
The common-mode gain of the differential amplifier will be small (desirable) if the small-signal
Norton, resistance rn of the biasing current source is large. The biasing current source is not a
naturally occurring element, but must be synthesized from other transistors. In most situations,
the designer will choose some form of current mirror to produce the equivalent current source.
The circuit on the left, shown below, is equivalent in all respects to the symbolic current-source
component on the right. In the current mirror circuit shown on the left, the reference current is
set by the resistor. The voltage across the latter is given by the voltage drop across because the
two MOSFETs are matched, and have precisely the same gate-source and threshold voltages
(vGSA = vGSB), their drain currents will be equal. Thus, the current I0 becomes a replica, or
"mirror image" of the reference current. As long as QB remains in its constant current region,
then this replication will take place. Note that QA automatically operates in its constant current
region, because it's gate is connected to its drain. The Norton resistance rn the current source
will be equal to the output resistance ro of QB, as determined by the upward slope of that
transistor's voltage-current characteristic.
65 | P a g e
Current Biasing MOSFETS:
In an Differential amplifier, we use current biasing MOSFET’s to keep all the FET’s in
saturation region.
To keep this MOSFET in saturation region we need to current mirror it with another
MOSFET.
If the biasing MOSFET is PMOS, then it’s mirror will also be PMOS.
If the biasing MOSFET is NMOS, then it’s mirror will also be NMOS.
The mirror PMOS’s source will be connected to voltage supply.
The mirror NMOS’s drain will be connected to voltage supply.
The figure shows a single stage differential amplifier. V1 and V2 are differential inputs
and M5 and M6 are mirroring MOSFETS. M1 here is the current biasing MOSFETS
because the current flowing through M1 is the summation of the current of BRANCH 1
and BRANCH 2.
The mirror of M1 is M2 which ones drain is connected to M7 which is acting as a current
source (idc).
66 | P a g e
ICMR+ and ICMR- :
Input common-mode range (ICMR) is the range of common-mode voltages over which the
differential amplifier continues to sense and amplify the difference signal with the same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all MOSFETs
remain in the saturation region.
ICMR+ > All MOSFET saturation > ICMR-
Common mode rejection ratio (CMRR)
CMRR is a measure of how well the differential amplifier rejects the common-mode input
voltage in favor of the differential-input voltage.
CMRR =
Differe ntial mode voltage gain
Common mode voltage gain
The differential-mode input voltage = v1 - v2.
The common-mode input voltage =
v1+ v2
2
Output offset voltage VOS(out)
The output offset voltage is the voltage which appears at the output of the differential
amplifier when the input terminals are connected together.
Input offset voltage VOS(in)
The input offset voltage is equal to the output offset voltage divided by the differential
voltage gain.
VOS(in) =
𝑉𝑂𝑆(𝑜𝑢𝑡 )
𝐴𝑣
5.10 Slew Rate
Slew rate is the maximum voltage change per unit time in a node of a circuit, due to
limited current sink or source.
Explanation:
The figure shows a differential amplifier with a
load capacitor Cload. Input V+ and V- and
supply voltage Vdd and ground.
Now,
 V+ and V- are inverse sinewave.
 If we increase V+, V- decreases.
67 | P a g e
 If we increase V-, V+ decreases.
 Step 1 :
 Increase V- , so at a point V+ will be ≈ 0.
 No current will flow through branch 1.
 All current will flow through branch 2.
 Cload will be charged.
 Step 2:
 Increase V+ , so at a point V- will be ≈ 0.
 No current will flow through branch 2.
 All current will flow through branch 1.
 Cload will be discharged.
The rate of charge of charging or discharging of capacitor is typically known as Slew
rate.
Itotal = Cload x Slew Rate = Cload x c
𝑑𝑣𝑐
𝑑𝑡
5.11 Common source, Common Gate, Common Drain amplifiers:
68 | P a g e
Common Source, Common Gate, Common Drain amplifier:
Common source: Typically known as Voltage amplifier, It has higher input resistance
and lower gain than CE amplifier.
The voltage gain is given by the equation Av = gmRd.
Rd is the resistance between drain to supply voltage.
Characteristics (small signal):
Common Drain: Used as Voltage buffer, also used for
transform impedances.
The voltage gain is given by the equation
Small Signal Characteristics:
1
m s
v
m s
g R
A
g R


69 | P a g e
Common Gate: Typically used as a current buffer or voltage amplifier. The
analogous bipolar junction transistor circuit is the common-base amplifier.
Characteristics:
5.12 Designing in Cadence:
From the previous chapter, we got the design of LVD, HVD. To design those parts in
Cadence, we need to design:
1. And Gate & And gate Layout
2. Or Gate & Or gate Layout
3. Inverter & Inverter layout
4. Comparator & Comparator Layout
AND GATE:
Calculations:
Pull Down Part:
120
100
+
120
100
=
120
200
(as though the FET’s are in series, their length will be
added)
=
240
100
(each)
Pull up Part:
= 3 x
240
100
=
720
100
=
360
100
(each)
70 | P a g e
Logic:
F = A.B
= 𝐴. 𝐵 = 𝐴 + 𝐵
= 𝐴 + 𝐵 (inverter)
= A.B
Schematic
71 | P a g e
Layout:
Height = 3μ
Length = integer of 0.3μ
Height of Vdd and Vss = 0.53μ
OR GATE:
Calculations:
Pull Down Part:
120
100
+
120
100
=
240
100
(as though the FET’s are in parallel, their width will be
added) =120/100 (each)
Pull up part = 3 x
240
100
=
720
100
=
360
100
(each)
72 | P a g e
Logic:
F = A + B
= 𝐴 + 𝐵 = 𝐴 . 𝐵
= 𝐴 . 𝐵 (inverter)
= A + B
Schematic:
73 | P a g e
Layout:
Height = 3μ
Length = integer of 0.3μ
Height of Vdd and Vss = 0.53μ
74 | P a g e
5.13 Comparator:
COMPARATOR WORKING PRINCIPLE:
When
 Variable i/p is at V1
 VREF is at V2
 If V1>V2, then o/p= +Vcc
else
o/p= -Vcc
75 | P a g e
Challenges to design comparator:
 Remove feedback of non-inverting OPAMP and turn it into comparator.
 Meet of some conditions.
 Keep gain at least Av = ~10,000
 Suitable for this design.
Conditions:
 Slew Rate = 10v/μs
 VDD = 1.8 V
 VSS = 0 V
 o/p swing = 1.8 V
 ICMR+ = 1.6 V
 ICMR- = 1.4 V
 Vout = 0 < 1.8
Comparator Block Diagram:
76 | P a g e
5.14 Calculations:
Cload = 2pF
ID7 = CL x SR = (2 x 10^-12)(10^6)
= 20 μA
VDS7(SAT) = Vo(min) – Vss = 0 – 0 = 0 ≈ 0.5v
VDS7(SAT) =
2𝐼𝐷𝑆7
𝛽7
=
2𝐼𝐷𝑆7
𝐾𝑁
𝑊
𝐿
7

𝑊
𝐿
7 = {
2𝐼𝐷𝑆7
𝐾𝑁( 𝑉𝐷𝑆(𝑆𝐴𝑇 2)
}^2
 = {
2(20𝑥10−6)
344.16𝜇( 0.5 2)
} ^2 ( βN = 413μ and initial w/L= 1.2)

 = 0.46
Now, VDS6(SAT) ≈ 0.5

𝑊
𝐿
6 = {
2𝐼𝐷𝑆6
𝐾𝑃( 𝑉𝐷𝑆(𝑆𝐴𝑇 2)
}^2
= {
2(20𝑥10−6)
264𝜇( 0.5 2)
} ^2 ( βP = 366μ and initial w/L= 1.2)
 = 0.6
Considering initial ( 𝑊
𝐿)4 =1.2 to determine current ISD4 which is mirror with M6.
ISD4 =
( 𝑊
𝐿)4
( 𝑊
𝐿)6
ISD6 =
1.2
0.6
(20μ) = 40μ
Considering initial ( 𝑊
𝐿)5 = 1.2 to determine current ISD4 which is mirror with M7.
ISD5 =
( 𝑊
𝐿)5
( 𝑊
𝐿)6
ISD6 =
1.2
0.4
(20μ) = 60μ
ISD4 =
𝐼𝐷𝑆5
2
= 30μ = ISD3
77 | P a g e
IDS2 = IDS1 =
𝐼𝐷𝑆5
2
= 30μType equation here.
( 𝑊
𝐿)4 =
𝐼𝑆𝐷4
𝐼𝑆𝐷6
( 𝑊
𝐿)6 =
30𝜇
20𝜇
(0.6) = 0.72
𝑁𝑂𝑊
𝑊
𝐿
5 =
2𝐼𝐷𝑆5
𝐾𝑁 𝑉𝐷𝑆 𝑆𝐴𝑇 ^2
VDS5(SAT) = VGI(MIN)-VSS-
2𝐼𝐷𝑆1
𝐾𝑁( 𝑊
𝐿)1
- VT1
= 1.4 - 0 -
2(30𝜇)
344.16𝜇(1.2)
- 0.7
= 0.56 V
So,
𝑊
𝐿
5 =
2(60𝜇)
344.16𝜇 0.56 ^2
= 1.22
VGI(MAX) = VDD -
2𝐼𝑆𝐷3
𝐾𝑃( 𝑊
𝐿)3
- VT3 + VT1
 ( 𝑊
𝐿)3 =
2𝐼𝑆𝐷3
𝐾𝑃 𝑉𝐷𝐷−𝑉𝐺1 𝑀𝐴𝑋 −𝑉𝑇3+𝑉𝑇1 2
 =
2(30𝜇)
264𝜇 1.8−1.6−0.7+0.7 2
 = 5.68
Now, M9 working as a current source,
(𝑊
𝐿)3 = 1
After ADE L simulation, to get perfect (W/L) ratio for all MOSFETS:
M1 M2 M3 M4 M5 M6 M7 M8 M9
( 𝑊
𝐿) 0.81 0.81 1.09 1.09 0.81 9 3.35 3.35 1
Calculations of Second Stage Gain :
Av2 =
2𝐾𝑃𝐼𝑆𝐷6( 𝑊
𝐿)6
𝐼𝑆𝐷6(𝜆𝑃+𝜆𝑁)
=
2 264𝜇 (20𝜇)(9)
(20𝜇)(0.005+0.005)
≈ 100
So, the first stage gain will be Av1Av2=10,000
So, Av2= 100.
Schematic of comparator:
78 | P a g e
Schematic(Cellview):
79 | P a g e
Output:
Layout: For layout, we eliminated the capacitor because of design. And also, the design
has cap for itself without the load capacitor.
80 | P a g e
5.15 HVD(High Voltage Disconnect):
The HVD part is shown below:
81 | P a g e
Layout of the logic part:
Layout of whole part:
82 | P a g e
5.16 LVD (Low Voltage Disconnect)
Layout:
83 | P a g e
Conclusion:
This study presents whole description of component like solar panel, solar
charge controller. Proteus simulation if whole system is shown here. As, our
aim was to design a solar charge controller using analog components, we
explained our calculations and simulations in cadence analog designing. We
showed the HVD and LVD parts both in Cadence and Proteus, We connected
them and showed that the whole design works. At last, we completed the
Layout for each design and connected them. This design is energy and area
efficient. It consumes less power and can be implemented in mot designs. This
system can be modified by further research and could be used in modern
technologies.
84 | P a g e
References:
https://en.wikipedia.org/wiki/
http://webpages.eng.wayne.edu/
http://www.csee.umbc.edu/
http://electronics.stackexchange.com/
https://inst.eecs.berkeley.edu/
http://ecee.colorado.edu/
https://www.quora.com/
http://www.electronics-tutorials.ws/
https://www.youtube.com/
http://ic.sjtu.edu.cn/ic/wp-content/uploads/sites/10/2013/04/CMOS-VLSI-
design.pdf
Bahzad Razavi Book : Design of Analog CMOS integrated circuit.

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  • 1. 1 | P a g e DESIGN AND IMPLEMENTATION OF SOLAR CHARGE CONTROLLER IC USING CADENCE. A Thesis Submitted to the Department of Electrical And Electronic Engineering in partial Fulfillment of the Requirement for the Degree of Bachelor of Science in Electrical and Electronic Engineering (EEE) Department of Electrical and Electronic Engineering United International University, Dhaka, Bangladesh June, 2016
  • 2. 2 | P a g e A Thesis on DESIGN AND IMPLEMENTATION OF SOLAR CHARGE CONTROLLER IC USING CADENCE. Submitted By- MD. Aktarul Islam ID: 021 121 050 Email: rahul.aktarul@gmail.com MD. Abdur Rahim ID: 021 121 051 Email: rahimuiu@gmail.com Abdul Fattah ID : 021 121 082 Email: abdu_92@yahoo.com Sumaiya siddiquea ID : 021 121 083 Email: sumaiyariya@gmail.com Supervisor: Dr. Md. Iqbal Bahar Chowdhury Email: ibchy@eee.uiu.ac.bd Associated Professor, United International University
  • 3. 3 | P a g e Dedication To our honorable Parents and faculties …………..
  • 4. 4 | P a g e Declaration It is hereby declared that this thesis or any part of it has not been submitted elsewhere for the award of any degree or diploma. Signature of the Supervisor: …………………………..………………………………… Dr. Md. Iqbal Bahar Chowdhury Signature of the Candidates: ……..…………………………………. Md. Aktarul Islam ………………………………………….. Md. Abdur Rahim …………………………………... Abdul Fattah ………………………………….. Sumaiya siddiquea
  • 5. 5 | P a g e Acknowledgements The students, researchers and authors of this book are happy and delighted to entitle the names of those who have worked hard to complete the project entitled “DESIGN AND IMPLEMENTATION OF SOLAR CHARGE CONTROLLER IC USING CADENCE.”. At first, our gratitude goes to our Almighty Allah without whose blessings it is impossible to finish the tasks we were entrusted with. We are also very much thankful to our parents for their unconditional love, sincere advice, care and support that have helped us to step into the step door of manhood. Authors are greatly indebted to the supervisor of the project, Dr. Md. Iqbal Bahar Chowdhury, Associated Professor, Dept. of EEE, UIU whose encouragement, guidance and suggestions from the initial point to the final phase enabled us to develop an understanding on the subject and made us capable to complete this work successfully. Special thanks to all of our friends for their support and encouragements. A number of ideas generated from our numerous discussions are incorporated in this thesis.
  • 6. 6 | P a g e Abstract Nowadays, solar charge controller plays the vital role in renewable energy section to protect and serve the PV system. All over the world, for energy controlling, mankind uses different solar charge controllers. But, the price of solar charge controller is high because it generally uses microcontrollers and PCB boards which consume energy and space. Our main tasks were to replace the microcontrollers using analog transistors and MOSFET’s which are measured in nanometers and consumes really low energy and works in high frequency. To complete the tasks, first we divided the area of charge controller system, simulated the design and confirmed it’s working through proteus software. Then we calculated the parameters of the controller parts and implemented in cadence virtuoso tool. After successful simulation, we created its Layout and connected them as the logic system.
  • 7. 7 | P a g e CONTENT Page No. Chapter 1 1.1 Objective 1.2 Scope 1.3 Organization 10 10 11 Chapter 2 : Overview of Solar Photovoltaic 2.1 Overview of solar PV system 2.2 Charge Transport in the Doped Silicon 2.3 Fundamental of solar cell 2.4 Effects of a P-N junction 2.5 Cell Structure 2.6 Charge transport in silicon solar cell 2.7 Theoretical Description of solar cell 2.8 Influence of Series and parallel resistance 2.9 Sources of losses in solar cell 2.10 Common Types of solar cell 11 12 13 14 16 17 17 19 21 22 Chapter 3 : Overview of Solar charge controller 3.1 Charge Controller 3.2 Function of charge controller 3.3 Types of charge controller 3.4 Parallel Controller 3.5 Series Controller 3.6 Panel Charging and characteristics of controller 3.7 Charge Controller operation 3.8 Selection of Charge Controller 3.9 Voltage setting of controller 3.10MPPT Charge controller 3.11 Solar home system design with charge controller 25 26 26 26 27 28 28 29 29 30 31 Chapter 4 : Challenges of implementation of a solar charge controller in Cadence 4.1 Switching Algorithm of solar charge controller 4.2 Step to implement the switching Algorithm of solar charge controller 4.3 Overview of working principle of Blocks of charge controller IC 4.4 Voltage compare units 4.5 Logic Units 4.6 Proteus Simulation 33 34 35 35 39 47 Chapter 5 : Cadence Implementation 5.1 About Cadence 5.2 Cadence Library 5.3 About Virtuoso tool 5.4 About Virtouso Layout Suit 5.5 Scale Calculations 48 49 49 50 51
  • 8. 8 | P a g e 5.6 Analog Design Parameter 5.7 Regions of MOSFET operation 5.8 CMOS Basics 5.9 Differential Amlifier 5.10 Slew Rate 5.11 Common Source, common gate, common drain amplifier 5.12 Designing in Cadence 5.13 Comparator 5.14 Calculations 5.15 HVD 5.16 LVD 51 57 60 63 66 67 69 74 76 80 82 Chapter 6 : Conclusion 83 References 84
  • 9. 9 | P a g e
  • 10. 10 | P a g e CHAPTER 1 Introduction: Solar Charge Controller components (Comparator, Microcontroller, Resistance e.t.c) are being packaged into one single IC. Successfully simulated with Proteus initially, then implemented in virtuoso(Schematic and Layout) using CMOS . 1.1 Objective Solar charge controller helps to prevent batteries from overcharging. For some good quality solar charge controllers, they helps to lengthen the effective lifespan of batteries. A normal solar panel rated at 12V- 14V may be producing 16V to 18V at peak sun. A charge controller helps to regulate the charging process of batteries, preventing overcharging. It also helps to prevent electricity from flowing from the batteries to the solar panels at night. Solar charge controller also helps to get the most out of a solar panel. This is by utilizing MPPT(Maximum power point tracking) or PWM (Pulse Width Modulation). MPPT solar charge controller monitors the voltage and current output of the solar panel and determines the voltage that the panel will produce at the maximum efficiency. PWM helps to “pamper” batteries by providing constant voltage battery charging, hence prolonging battery life. The batteries are very expensive. It is not worth it to throw them away due to overcharging. Hence, by doing a research and finding a good quality charge controller was our objective that can save batteries and let a solar panel to work upto its fullest potential. 1.2 Scope In this work, an analog model of solar charge controller has been designed. Commercially available solar charge controller has a microcontroller which controls different voltage levels. But these available charge controller in market places have two serious issues with cost n area. We were assigned to replace the commercially available microcontroller based solar charge controller by implementing the whole design on a single IC using Cadence. The other part of assignment is to enhance the charge controller performance. A methodology should be developed and verify so that the efficiency of the charge controller is increased keeping the cost and area at optimum level.
  • 11. 11 | P a g e 1.3 Organization This thesis book is consisting of five chapters. The whole work is organized in the subsequent chapters as follows. Chapter 1 describes the introduction on charge controller in general. It provides a literature review on charge controller. Finally objective, scope of work and organization of thesis have been provided in this chapter. In chapter two the basic overview of a solar charge controller is described. In chapter three challenges of implementing a solar charge controller in a IC are described. In chapter four cadence implementation, parameter calculation, block wise design are discussed sequentially where schematic design, waveforms, layout and DRC versus LVS are also shown. Chapter five gives the concluding remarks. CHAPTER 2 Overview of Solar Photovoltaic 2.1 Overview The direct transformation from the solar radiation energy into electrical energy is possible with the photovoltaic effect by using solar cells . The term photovoltaic is often abbreviated to PV. The radiation energy is transferred by means of the photo effect directly to the electrons in their crystals. With the photovoltaic effect an electrical voltage develops in consequence of the absorption of the ionizing radiation. Solar cells must be differentiated from photocells whose conductivity changes with irradiation of sunlight. Photocells serve e.g. as exposure cells in cameras since their electrical conductivity can drastically vary with small intensity changes. They produce however no own electrical voltage and need therefore a battery for operation. The photovoltaic effect was discovered in 1839 by Alexandre Edmond Becquerel while experimenting with an electrolytic cell made up of two metal electrodes. Becquerel found that certain materials would produce small amounts of electric current when exposed to light. About 50 years later Charles Fritts constructed the first true solar cells using junctions formed by coating the semiconductor selenium with an ultrathin, nearly transparent layer of gold. Fritts‟s devices were very inefficient: efficiency less than 1 %. The first silicon solar cell with an efficiency of approx. 6% was developed in 1954 by three American researchers, namely Daryl Chapin, Calvin Fuller and G.L. Pearson in the Bell Laboratories. Solar cells proved particularly suitably for the energy production for satellites in space and still represent today the exclusive energy source of all space probes. The interest in terrestrial applications has increased since the oil crisis in 1973. Main objective of research and development is thereby a drastic lowering of the manufacturing costs and lately also a substantial increase of the efficiency. The base material of almost all solar cells for applications in space and on earth is silicon. The most common structure of a silicon solar cell is schematically represented in Figure 3-1:
  • 12. 12 | P a g e Figure 3-1: Schematic drawing of a silicon solar cell [1, 2] An approx. 300 μm silicon wafer consists of two layers with different electrical properties prepared by doping foreign atoms such as boron and phosphorous. The back surface side is total metalized for charge carrier collection whereas on the front, which exposes to the beam of incident light, only one metal grid is applied in order that as much light as possible can penetrate into the cell. The surface is normally provided with an antireflection coating to keep the losses from reflection as small as possible. 2.2 Charge Transport in the Doped Silicon Now we consider the doping of silicon, a tetravalent element, which is the most frequent applied semiconductor material, also for solar cells. Replacement of a silicon atom by a pentavalent atom (Fig. 3-2a), e.g. phosphorus (P) or arsenic (As), leads to a surplus electron only loosely bound by the Coulomb force, which can be ionized by an energy (ca. 0.002 eV). The quantity eV is an energy unit corresponding to the energy gained by an electron when its potential is increased by one volt. Since pentavalent elements donate easily an electron, one calls them donors. The donor atom is positively charged with the electron donation (ionized). The current transport in such a material practically occurs only by means of electrons, it is called n-type material.
  • 13. 13 | P a g e Figure 3-2: Doping of silicon (a) with pentavalent atom (b) with trivalent atom Replacement by a trivalent element (Fig. 3-2b), e.g. boron (B), aluminium (Al) or gallium (Ga), leads to a lack of an electron. Now an electron in the neighborhood of a hole can fill up this blank and leaves a new hole at its original position consequently. This results in the current conduction by means of positive holes. Therefore this material is called p-type material. Trivalent atoms, which easily accept an electron, are defined as acceptors. The acceptor atoms are negatively ionized by the electron reception. At ambient temperature donors and acceptors are already almost completely ionized in the silicon. 2.3 Fundamental of solar cell The back surface side is total metalized for charge carrier collection where as on the front which expose to the beam of incident light. The surface is normally provided with an antireflection coating to keep the losses from reflection as small as possible
  • 14. 14 | P a g e 2.4 Effects of a P-N Junction Usually a p-n junction is generated by the fact that a strong n-type layer is produced in the p type material by in diffusion of a donor (P, As) at higher temperatures (ca. 850 °C). Completely analog in the n-type material, although less common, a p-n junction can be produced by in diffusion of an acceptor. In the boundary surface‟s neighborhood of the n- or p-type material the following effects occur: In the n-region so many electrons are available, in the p-region so many holes. These concentration differences lead to the fact that electrons from the n-region diffuse into the p region and holes from the p-region diffuse into the n-region. As a result, diffusion currents of electrons into the p-region and diffusion currents of holes into the n-region arise (Fig. below). By the flow of negative and positive charges a deficit of charges develops within the before electrically neutral regions, i.e. it results a positive charge within the donor region and a negative charge within the acceptor region.
  • 15. 15 | P a g e Figure: Charge carrier distribution at p-n junction and currents through the junction Thus an electrical field develops over the boundary surface and causes now field currents from both charge carrier types, which are against the diffusion currents. In the equilibrium the total value of current through the boundary surface is zero. The field currents compensate completely the diffusion currents: the hole currents compensate completely among themselves and the electron currents likewise. This electrostatic field extending over the boundary surface refers to the potential difference VD, which is called diffusion voltage . It is situated in the order of magnitude of 0.8 eV. This electrical field causes the separation of the charge carriers produced by light in the solar cell. Within the region of the stationary electrical positive and negative charge, in the so-called space- charge zone , a lack of mobile charge carriers appears, which has very high impedance. Applying the n-region with a negative voltage (forward bias) reduces the diffusion voltage, decreases the electrical field strength and thus the field currents. These do not compensate now the diffusion currents of the electrons and holes, as without external voltage, anymore. As a result a net diffusion current from electrons and holes flows through the p-n junction. If the applied voltage is equal to the diffusion voltage, then the field currents disappear and the current is limited only by the bulk resistors. Contrarily, an applied positive voltage at the outside n-region (reverse bias) adds itself to the diffusion voltage, increases the space-charge zone, thus it comes to outweighing the field current. The resulting current whose direction of the reverse bias is contrary is very small.
  • 16. 16 | P a g e 2.5 Cell structure Substrate Material (usually silicon) Bulk crystalline silicon dominates the current photovoltaic market, in part due to the prominence of silicon in the integrated circuit market. Cell Thickness (100-500 μm) An optimum silicon solar cell with light trapping and very good surface passivation is about 100 μm thick. Doping of Base (1 Ω·cm) A higher base doping leads to a higher Voc and lower resistance, but higher levels of doping result in damage to the crystal. Reflection Control (front surface typically textured) The front surface is textured to increase the amount of light coupled into the cell. Emitter Dopant (n-type) N-type silicon has a higher surface quality than p-type silicon so it is placed at the front of the cell where most of the light is absorbed. Thus the top of the cell is the negative terminal and the rear of the cell is the positive terminal. Emitter Thickness (<1μm) A large fraction of light is absorbed close to the front surface. By making the front layer very thin, a large fraction of the carriers generated by the incoming light are created within a diffusion length of the p-n junction Doping Level of Emitter (100 Ω) The front junction is doped to a level sufficient to conduct away the generated electricity without resistive loses. However, excessive levels of doping reduces the material's quality to the extent that carriers recombine before reaching the junction. Grid Pattern (fingers 20 to 200μm width, placed 1 – 5 mm apart) The resistivity of silicon is too low to conduct away all the current generated, so a lower resistivity metal grid is placed on the surface to conduct away the current. The metal grid shades the cell from the incoming light so there is a compromise between light collection and resistance of the metal grid. Rear Contact. The rear contact is much less important than the front contact since it is much further away from the junction and does not need to be transparent. The design of the rear contact is becoming increasingly important as overall efficiency increases and the cells become thinner.
  • 17. 17 | P a g e 2.6 Charge transport In silicon solar cell Effect of P-N junction  An electrical field developed over the Boundary surface causes field current From both charge carrier. The mathematical process at the p-n Junction leads to the famous diode Equation. Where, Io= Diode current (A), q= the electron charge v= applied voltage k= Boltzman constant T = Room temperature (K) 2.7 Theoretical Description of the Solar Cell As already mentioned, illuminated solar cell creates free charge carriers, which allow current to flow through a connected load. The number of free charge carriers is proportional to the incident radiation intensity. So does also the photocurrent (Iph), which is internally generated in the solar cell. Therefore an ideal solar cell can be represented by the following simplified equivalent circuit (Fig. below). It consists of the diode created by the p-n junction and a photocurrent source with the magnitude of the current depending on the radiation intensity. An adjustable resistor is connected to the solar cell as a load. The mathematical process of an ideal exposed solar cell leads to the following equation: Figure: Equivalent circuit diagram of an ideal solar cell connected to load
  • 18. 18 | P a g e In an imaginary experiment, the I-V characteristic curve for a certain incident radiation will now be constructed, point for point (Fig. below): Figure: Construction of the solar cell curve from the diode curve. Figure: Equivalent circuit diagram of the solar cell – short-circuit current. When the terminals are short-circuited (Rload = 0 ) (Fig. above), the output voltage and thus also the voltage across the diode is zero. Since V = 0 , no current ID flows (point 1 in Figure 3-6)
  • 19. 19 | P a g e therefore the entire photocurrent Iph generated from the radiation flows to the output. Thus the cell current has its maximum at this point with the value Icell and refers to the so-called short- circuit current Isc . Isc = Icell = Iph 2.8 Influence of series- and parallel resistance With regard to the behavior of a real solar cell, two parasitic resistances inside the cell, namely a series- (Rs) and parallel resistance (Rp), are taken into consideration for more exact description as indicated in the equivalent circuit diagram in Figure below. Figure: Equivalent circuit diagram of a real solar cell The series resistance arises from the bulk resistance of the silicon wafer, the resistance of the metallic contacts of the front- and back surface and further circuit resistances from connections and terminals. The parallel resistance is mainly caused by leakage currents due to p-n junction non-idealities and impurities near the junction, which cause partial shorting of the junction, particularly near the cell edges.
  • 20. 20 | P a g e Figure: I-V curve for different series resistances (Source: Kassel University) Figure : I-V curve for different parallel resistances (Source: Kassel University)
  • 21. 21 | P a g e Only larger series resistances reduce also the short-circuit current whereas very small parallel resistances reduce the open-circuit voltage. However, their influence reduces primarily the value of the Fill factor (Fig. 3-11, Fig. 3-12). As a result, the maximum power output is decreased. 2.9 Sources of losses in solar cells a) A part of the incident light is reflected by metal grid at the front. Additional reflection losses arise during radiation transition from the air into the semiconductor material due to different indexes of refraction. These losses are reduced by coating the surface with antireflection layer. Another possibility is a structuring the cell surface. b) The solar radiation is characterized by a wide spectral distribution, i.e. it contains photons with extreme different energies. Photons with small energy than the band gap are not absorbed and thus are unused. Since the energies are not sufficient to ionize electrons, electron-hole pairs will not be produced. In case of photons with larger energy than the band gap, only amount of energy equal to the band gap is useful, regardless of how large the photon energy is. The excess energy is simply dissipated as heat into the crystal lattice. c) Since the photocurrent is directly proportional to the number of photons absorbed per unit of time, the photocurrent increases with decreasing band gap. However, the band gap determines also the upper limit of the diffusion voltage in the p-n junction. A small band gap leads therefore to a small open-circuit voltage. Since the electrical power is defined by the product of current and voltage, a very small band gaps result in small output power, and thus low efficiencies. In case of large band gaps, the open-circuit voltage will be high. However, only small part of the solar spectrum will be absorbed. As a result, the photocurrent achieves here only small values. Again, the product of current and voltage stays small. d) The dark current I0 is larger than the theoretical value. This reduces the open-circuit voltage. e) Not all charge carriers produced are collected, some recombine. Charge carriers recombine preferably at imperfections, i.e. lattice defects of crystal or impurities. Therefore, source material must have a high crystallographic quality and provide most purity. Likewise, the surface of the semiconductor material is a place, in which the crystal structure is very strongly disturbed, and forms a zone of increasing recombination. f) The Fill factor is always smaller than one (theoretical max. value ca. 0.85). g) Series- and parallel resistance result in reduction of the Fill factor [1, 2, 4].
  • 22. 22 | P a g e 2.10 Common Types of Solar Cells Hundreds of solar cells (also called photovoltaic cells) make up a solar photovoltaic (PV) array. Solar cells are the components of solar arrays that convert radiant light from the sun into electricity that is then used to power electrical devices and heat and cool homes and businesses. Solar cells contain materials with semiconducting properties in which their electrons become excited and turned into an electrical current when struck by sunlight. While there are dozens of variations of solar cells, the two most common types are those made of crystalline silicon (both monocrystalline and polycrystalline) and those made with what is called thin film technology. Silicon Solar Cells The majority of the solar cells on the market today are made of some type of silicon - by some estimates, 90% of all solar cells are made of silicon. However, silicon can take many different forms. Variations are most distinguished by the purity of the silicon; purity in this sense is the way in which the silicon modules are aligned. The greater the purity of the silicon molecules, the more efficient the solar cell is at converting sunlight into electricity. The majority of silicon based solar cells on the market - about 95% - are comprised of crystalline silicon, making this the most common type of solar cell. But there are two types of crystalline - monocrystalline and polycrystalline. Monocrystalline Silicon Solar Cells Monocrystalline solar cells, also called "single crystalline" cells are easily recognizable by their coloring. But what makes them most unique is that they are considered to be made from a very pure type of silicon. In the silicon world, the more pure the alignment of the molecules, the more efficient the material is at converting sunlight into electricity. In fact, monocrystalline solar cells are the most efficient of all; efficiencies have been documented at upwards of 20%. Monocrystalline solar cells are made out of what are called "silicon ingots," a cylindrically shaped design that helps optimize performance. Essentially, designers cut four sides out of cylindrical ingots to make the silicon wafers that make up the monocrystalline panels. In this way, panels comprised of monocrystalline cells have rounded edges rather than being square, like other types of solar cells. Beyond being most efficient in their output of electrical power, monocrystalline solar cells are also the most space-efficient. This is logical since you would need fewer cells per unit of electrical output. In this way, solar arrays made up of monocrystalline take up the least amount of space relative to their generation intensity.
  • 23. 23 | P a g e Another advantage of monocrystalline cells is that they also last the longest of all types. Many manufacturers offer warranties of up to 25 years on these types of PV systems. The superiority of the monocrystalline cells comes with a price tag - in fact, solar panels made of monocrystalline cells are the most expensive of all solar cells, so from an investment standpoint, polycrystalline and thin film cells are often the preferred choice for consumers. One of the reasons monocrystalline cells are so expensive is that the four sided cutting process ends up wasting a lot of silicon, sometimes more than half. Polycrystalline Solar Cells Polycrystalline solar cells, also known as polysilicon and multisilicon cells, were the first solar cells ever introduced to the industry, in 1981. Polycrystalline cells do not go through the cutting process used for monocrystalline cells. Instead, the silicon is melted and poured into a square mold, hence the square shape of polycrystalline. In this way, they're much more affordable since hardly any silicon is wasted during the manufacturing process. However, polycrystalline is less efficient than its monocrystalline cousin. Typically, polycrystalline solar PV system operated at a 13-16% efficiency - again, this is due to the fact that the material has a lower purity. Due to this reality, polycrystalline is less space-efficient, as well. One other drawback of polycrystalline is that has a lower heat tolerance than monocrystalline, which means they don't perform as efficiently in high temperatures. Thin Film Solar Cells Another up and coming type of solar cell is the thin film solar cell with growth rates of around 60% between 2002 to 2007. By 2011, the thin film solar cell industry represented approximately 5% of all cells on the market. While many variations of thin film products exist, they typically achieve efficiencies of 7-13%. However, a lot of research and development is being put into thin film technologies and many scientists suspect efficiencies to climb as high as 16% in coming models. Thin film solar cells are characterized by the manner in which various type of semi-conducting materials (including silicon in
  • 24. 24 | P a g e some cases) are layered on top of one another to create a series of thin films. The major draw of thin film technologies is their cost. Mass production is much easier than crystalline-based modules, so the cost of mass producing thin film solar cells is relatively cheap. The product itself is also flexible in nature, which is leading to many new applications of solar technologies in scenarios where having some type of flexible material is advantageous. Another perk is that high heat and shading have less of a negative impact on thin film technologies. For these reasons, the thin film market continues to grow. One major drawback is that thin film technologies require a lot of space. This makes them less of an ideal candidate for residential applications where space become an issue; as a result, thin film is taking off more in the commercial space. And thin film solar cells have a shorter shelf life than their crystalline counterparts, which is evidence by the shorter warranties offered by manufacturers. Thin film technology using various photovoltaic substances, including amorphous silicon, cadmium telluride, copper indium and gallium selenide. Each type of material is suitable for different types of solar applications. Amorphous Silicon Solar Cells Thin film solar cells made out of amorphous silicon are traditionally used for smaller-scale applications, including things like pocket calculators, travel lights, and camping gear used in remote locations. A new process called "stacking" that involves creating multiple layers of amorphous silicon cells have resulted in higher rates of efficiency (up to 8%) for these technologies; however, it's still fairly expensive. Cadmium Telluride Solar Cells Cadmium Telluride is the only of the thin-film materials that have been cost-competitive with crystalline silicon models. In fact, in recent years, some cadmium models have surpassed them in terms of their cost-effectiveness. Efficiency levels result in a range of 9-11%. Copper Indium Gallium Selenide Solar Cells Copper Indium Gallium Selenide cells have demonstrated the most promise with respect to their efficiency levels that range from 10-12%, somewhat comparable to crystalline technologies. However, these cells are still in the nascent stages of research and have been commercial deployed on any wide scale. That said, the technology is most used in larger or commercial applications.
  • 25. 25 | P a g e CHAPTER 3 Overview of Charge Controller 3.1 Charge Controller: Charge controller is an electronic device which is used in solar system. A solar charge controller is needed in virtually all solar power systems that utilize batteries. The job of the solar charge controller is to regulate the power going from the solar panels to the batteries. Overcharging batteries will at the least significantly reduce battery life and at worst damage the batteries to the point that they are unusable. The most basic charge controller simply monitors the battery voltage and opens the circuit, stopping the charging, when the battery voltage rises to a certain level. Older charge controllers used a mechanical relay to open or close the circuit, stopping or starting power going to the batteries. Modern charge controllers use pulse width modulation (PWM) to slowly lower the amount of power applied to the batteries as the batteries get closer and closer to fully charged. This type of controller allows the batteries to be more fully charged with less stress on the battery, extending battery life. It can also keep batteries in a fully charged state (called―float) indefinitely. PWM is more complex, but doesn„t have any mechanical connections to break. The electricity produced in the solar panel is stored in the battery. The electricity stored in the battery is used at night. This whole process is monitored by the charge controller. A typical charge controller (Phocos) is shown in the figure bellow Figure: Charge controller
  • 26. 26 | P a g e 3.2 Function of charge controller The main function of a charge controller or regulator is to fully charge a battery without permitting overcharge while preventing reverse current flow at night. Other functions are- Stop the process of the battery when it is fully charged. Disconnect the load during low voltage. Disconnect the load during high voltage. Monitor the battery voltage, state of charge, SOC etc. To give alarm during fault condition. Current measurement. Detect when no energy is coming from the solar panels and open the circuit, disconnecting the solar panels from the batteries and stopping reverse current flow. Charge controller is used for co-ordination and control among the battery, load and solar panel. Charge controller stores the electricity in the battery during day time and supplies the same to the load (mainly lamp) at night. On the other hand, if battery is fully charged, then charge controller can directly supply electricity to the load (Fan, mobile charger etc) from the solar panel during day time. A charge controller or charge regulator is mainly worked as a voltage regulator. Generally it controls the voltage and current of the solar panel to save in battery. Solar panel mainly produces 16 volts to 21 volt and 14 volt to 14.4 volt is required to keep the battery in full charged state. The charge controller works as a Buck converter to minimize this voltage level. Charge controller is mainly a Chopper or DC-DC converter. Buck converter is usually used in the solar panel which converts the high level DC voltage to the low level DC voltage. 3.3 Types of Charge controller Charge controller connection mainly two types- 1. Parallel or shunt controller 2. Series controller 3.4 Parallel Controller: Figure: Use of Shunt controller in solar home system
  • 27. 27 | P a g e In this system, charge controller is in parallel with the battery and load. When the battery is fully charged, then the solar panel is short circuited by the controller In this system, a ―Blocking diode is needed. So that reverse current would not flow from battery to thepanel. When the battery is charged through this blocking diode, it gets hot. Disadvantages of shunt controller:  Lose of electricity  When the panel is short circuited, huge amount of short circuit current flows through the switch (FET).  Shunt controller gets hotter compared to series controller.  There is a chance of hot spot on the panel. 3.5 Series Controller: Figure: Use of Shunt controller in solar home system In this system, charge controller is connected in between with the solar panel and battery. In order to terminate the flow of electricity to the battery, the series controller must be removed from the battery. There‟s no need of blocking diode in this system, but in many reasons it is used to terminate the process of discharging at night. The resistance should be maintained as low as possible in order to minimize lose of the electricity. Advantages of series controller: Blocking diode is not required. Series controller switch is handled with low voltage compared to shunt controller. Low switching noise. It is possible of precision charge and PWM of the battery. No chance of hot spot like the shunt controller .
  • 28. 28 | P a g e 3.6 Panel charging and characteristics of controller:Below figure shows how different kinds of charge controller controls the voltage andcurrent. The upper curve shows the battery voltage and the lower curve shows panel current. a,b,c,d indicates controller„s action . Below figure shows how different kinds of charge controller controls the voltage and current. The upper curve shows the battery voltage and the lower curve shows panel current. a,b,c,d indicates controller„s action . Figure: Relation between different types of charge controller and battery voltage and current 3.7 Charge Controller Operation: Fixed Set Point: To terminate the panel current when it reaches to the maximum voltage level and then continue it again when it reaches to the minimum voltage level is called ―Set point. The relation between charging-discharging of a battery and voltage is shown in the figure bellow-
  • 29. 29 | P a g e Figure: Set point of controller (Micro-controller based) There„s a possibility of the damage of the battery (50-100%) if the voltage level is set as the red dotted line of the above figure. We can match the controller„s voltage-current with the state of charge (SOC) by using micro-controller and Fuzz logic. This will reduce the probability of damaging the battery (10-20%). 3.8 Selection of charge controller Solid state series controller is suitable for small system (4 ampere). Solid state shunt controller is suitable for the system of 4 to 30 ampere. A good controller must have following features- Low voltage disconnection Battery charging current indicator (LED or meter). Battery voltage indicator (LED or meter). Sense lead. Adjustable set point. Ability of Communication (for large system). Data logger Computer interface 3.9 Voltage setting of controller The following factors are responsible for the voltage setting of controller- Types of battery Charging characteristics of charge controller Size of the battery Maximum panel current
  • 30. 30 | P a g e Figure: A solid state series controller and its various parts 3.10 MPPT Charge controller MPPT charge controller is a maximum power point tracker which is an electronic DC to DC converter which takes the DC input from the solar panels, changes it to high frequency AC and converts it back to a different DC current to match with the batteries. This is a solely electronic tracking system and not concerned with the panel system at all. Figure: Phocos MPPT 100/20(20 amps)
  • 31. 31 | P a g e 3.11 Solar home system design with charge controller The basic components are PV module, Charge controller, Battery, Inverter, Wire. For calculation first we need to know our demand and running hour. Think our demand is 200 W and duration of running hour is 4 hour. So 200* 4=800Wh.The formula of PV design is PV module = demand watt hours* de-rating factor /peak sun. Suppose peak sun is 4.5 hour de-rating factor is 1.3. So PV module =800*1.3/4.5 =231.111W. So we need three 85 Wp module which give 255W.The formula of PV calculation is Capacity of charge controller= demand watt *safety factor/system voltage= 200*1.25/12=20.83333A/12V.This result is fraction so we use 25A/12V charge controller. The formula of battery sizing is Battery capacity= demand Wh* Autonomy/efficiency*DOD*System voltage. Here DOD is depth of discharge and autonomy is number of day we use battery as abackup power. Suppose DOD is .6 and autonomy is 1 day, efficiency is 8. So, battery capacity =800*1/.8*.6*12 =138.888Ah.The calculation for inverter is Inverter = demand *safety factor=200*1.25 =250 W 220V Ac /12 V DC. Fig : Connecting diagram for dc current Fig: connecting diagram for ac
  • 32. 32 | P a g e CHAPTER 4 Challenges of implementation of solar charge controller in cadence In this chapter, we discuss about the challenges of implementing and design of a solar charge controller in Analog IC. A charge controller is required in most PV systems that use battery storage to regulate battery state-of-charge, optimize battery and system performance, and help prevent damage to the batteries or hazardous conditions resulting from the charging process. Figure: Simple block diagram of Charge controller. Functions of charge controllers include:  Battery overcharge and/or over discharge protection  Control of loads or other energy sources Features of charge controllers include:  Type of switching and control algorithm  Equalization charging
  • 33. 33 | P a g e Figure: Two main work of charge controller. 4.1 Switching Algorithm of solar charge controller Figure: Circuit block diagram of charge controller.
  • 34. 34 | P a g e This block diagram shows the main switching function of charge controller. Switch1 control the battery charging condition and switch 2 control the load condition. These two switches operate based on battery voltages that we concern i.e. 14.4v,13.8v,12.6v and 10.8v. These voltages based operation are shown in below table. Voltage value Switch 1 status Switch 2 status Priority Condition HVD >14.4 OFF D PV disconnected from the Battery. HVR <13.8 ON D PV connected to Battery. LVD <10.8 D OFF Battery disconnected from the load. LVR >12.6 D ON Battery connected to load. In this table, we can see that we consider four battery voltages point i.e.  HVD (High voltage disconnect)  HVR (High voltage re-connect)  LVD (Low voltage disconnect)  LVR (Low voltage re-connect) Mainly High voltages conditions is mainly used for sensing the charging condition and low voltages points are being concerned about loading condition. For this reason and simplify our design we used don‟t care condition, which is denoted by D. 4.2 Step to implement the Switching Algorithm of solar charge controller. Our main challenges are replacing the switching circuits with analog IC. To do this, we have to understand the main working principle of charge controller. What a charge controller mainly do? Charge controller mainly follow some step i.e.  Take input voltage from battery.  Compare voltage.  Execution of logic.  Take decision.  Execute Instruction.
  • 35. 35 | P a g e So, to design a solar charge IC, we have to follow the step. But we complete this step, we design and implement some block units and attach them in the last step. 4.3 Overview of working principle of Blocks of charge controller IC. Figure: Blocks of solar controller. We can see that there are four block units. i.e  Input  Voltage compare  Logic units or decision taking unit.  Execution unit or Output. Input and Output units are mainly very simple design. Here we use some voltage divider and deriver MOS to drive the load. To implement the block, we have to concern about the voltage compare units which compare the battery voltage and Logic units which take the controlling decision. 4.4 Voltage compare Units In this units, we compare the battery voltage with our ref. voltage. Use 4 voltage comparator to compare four battery voltage points (14.4v,13.8v,12.6v and 10.8v). After compare gives output value either VDD or GND.
  • 36. 36 | P a g e Voltage comparator: A dedicated voltage comparator will generally be faster than a general-purpose operational amplifier pressed into service as a comparator. A dedicated voltage comparator may also contain additional features such as an accurate, internal voltage reference, an adjustable hysteresis and a clock gated input. A dedicated voltage comparator chips such as LM339 is designed to interface with a digital logic interface (to a TTL or a CMOS). The output is a binary state often used to interface real world signals to digital circuitry. If there is a fixed voltage source from, for example, a DC adjustable device in the signal path, a comparator is just the equivalent of a cascade of amplifiers. When the voltages are nearly equal, the output voltage will not fall into one of the logic levels, thus analog signals will enter the digital domain with unpredictable results. To make this range as small as possible, the amplifier cascade is high gain. The circuit consists of mainly Bipolar transistors. For very high frequencies, the input impedance of the stages is low. This reduces the saturation of the slow, large P-N junction bipolar transistors that would otherwise lead to long recovery times. Fast small Schottky diodes, like those found in binary logic designs, improve the performance significantly though the performance still lags that of circuits with amplifiers using analog signals. Slew rate has no meaning for these devices. For applications in flash ADCs the distributed signal across eight ports matches the voltage and current gain after each amplifier, and resistors then behave as level-shifters. The LM339 accomplishes this with an open collector output. When the inverting input is at a higher voltage than the non-inverting input, the output of the comparator connects to the negative power supply. When the non-inverting input is higher than the inverting input, the output is 'floating' (has a very high impedance to ground). The gain of op amp as comparator is given by this equation V(out)=V(in) How to Use an Op Amp as a Voltage Comparator? A voltage comparator is an electronic circuit that compares two input voltages and lets you know which of the two is greater. It‟s easy to create a voltage comparator from an op amp, because the polarity of the op-amp‟s output circuit depends on the polarity of the difference between the two input voltages. Suppose that you have a photocell that generates 0.5 V when it‟s exposed to full sunlight, and you want to use this photocell as a sensor to determine when it‟s daylight. You can use a voltage comparator to compare the voltage from the photocell with a 0.5 V reference voltage to determine whether or not the sun is shining.
  • 37. 37 | P a g e In the voltage-comparator circuit, first a reference voltage is applied to the inverting input (V–); then the voltage to be compared with the reference voltage is applied to the noninverting input. The output voltage depends on the value of the input voltage relative to the reference voltage, as follows: Input Voltage Output Voltage Less than reference voltage Negative Equal to reference voltage Zero Greater than reference voltage Positive Note that the voltage level for both the positive and negative output voltages will be about 1 V less than the power supply. Thus, if the op-amp power supply is 9 V, the output voltage will be +8 V if the input voltage is greater than the reference voltage, 0 V if the input voltage is equal to the reference voltage, and –8 V if the input voltage is less than the reference voltage. You can modify the circuit to eliminate the negative voltage if the input is less than the reference by sending the output through a diode. In this circuit, a positive voltage appears at the output if the input voltage is greater than the reference voltage; otherwise, no output voltage exists.
  • 38. 38 | P a g e To create a voltage comparator that creates a positive voltage output if the input voltage is less than a reference voltage, apply the reference voltage to the inverting (V–) input, and the input voltage is applied to the noninverting (V+) input. The final voltage-comparator circuit you should know about is the window comparator, which lets you know whether the input voltage falls within a given range. A window comparator requires three inputs: a low reference voltage, a high reference voltage, and an input voltage. The output of the window comparator will be a positive voltage only if the input voltage is greater than the low reference voltage and less than the high reference voltage. If the input voltage is less than the low reference voltage, the output will be zero. Similarly, if the input voltage is greater than the high reference voltage, the output will also be zero. You need two op amps to create a window comparator. One op amp is configured to produce positive output voltage only if the input is greater than the low reference voltage (VREF(LOW)). The other op amp is configured to produce positive output voltage only if the input is less than the high reference voltage (VREF(HIGH)). The input voltage is connected to both op amps; the output voltage is sent through diodes to allow only positive voltage and then combined. The resulting output will have positive voltage only if the input voltage falls between the low and high reference voltages. In this unit, we design an op-amp based voltage comparator. We discuss the design and it‟s calculation in the next chapter.
  • 39. 39 | P a g e 4.5 Logic Units The logic unit, which take the input as digital value i.e. 5/0 from the comparator output, take the decision for charging condition and load control condition and finally, give a digital output which is our main output pin. Observing the voltage comparator output and considering our switching diagram we two same but separate logic for charging condition and load controlling condition. The schematic of logic circuits is given bellow: Figure: Logic circuit
  • 40. 40 | P a g e  Two Logic units for switch 1 and switch 2.  Logic circuits consist of an AND gate and OR gate. Now, we discuss the working principle of AND gate and OR gate. AND-Gate: A Logic AND Gate is a type of digital logic gate that has an output which is normally at logic level “0” and only goes “HIGH” to a logic level “1” when ALL of its inputs are at logic level “1”. The output state of a “Logic AND Gate” only returns “LOW” again when ANY of its inputs are at a logic level “0”. In other words, for a logic AND gate, any LOW input will give a LOW output. The logic or Boolean expression given for a digital logic AND gate is that for Logical Multiplication which is denoted by a single dot or full stop symbol, ( . ) giving us the Boolean expression of: A.B = Q. Then we can define the operation of a 2-input logic AND gate as being: “If both A and B are true, then Q is true” 2-input Transistor AND Gate A simple 2-input logic AND gate can be constructed using RTL Resistor-transistor switches connected together as shown below with the inputs connected directly to the transistor bases. Both transistors must be saturated “ON” for an output at Q.
  • 41. 41 | P a g e Logic AND Gates are available using digital circuits to produce the desired logical function and is given a symbol whose shape represents the logical operation of the ANDgate. Digital Logic “AND” Gate Types The 2-input Logic AND Gate Symbol Truth Table 2-input AND Gate B A Q 0 0 0 0 1 0
  • 42. 42 | P a g e 1 0 0 1 1 1 Boolean Expression Q = A.B Read as A AND B gives Q The 3-input Logic AND Gate Symbol Truth Table 3-input AND Gate C B A Q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0
  • 43. 43 | P a g e 1 0 1 0 1 1 0 0 1 1 1 1 Boolean Expression Q = A.B.C Read as A AND B AND C gives Q Because the Boolean expression for the logic AND function is defined as (.), which is a binary operation, AND gates can be cascaded together to form any number of individual inputs. However, commercial available AND gate IC‟s are only available in standard 2, 3, or 4-input packages. If additional inputs are required, then standard AND gates will need to be cascaded together to obtain the required input value, for example. Multi-input AND Gate The Boolean Expression for this 6-input AND gate will therefore be: Q = (A.B).(C.D).(E.F)
  • 44. 44 | P a g e OR-GATE: A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an output which is normally at logic level “0” and only goes “HIGH” to a logic level “1” when one or more of its inputs are at logic level “1”. The output, Q of a “Logic OR Gate” only returns “LOW” again when ALL of its inputs are at a logic level “0”. In other words, for a logic OR gate, any “HIGH” input will give a “HIGH”, logic level “1” output. The logic or Boolean expression given for a digital logic OR gate is that for Logical Addition which is denoted by a plus sign, ( + ) giving us the Boolean expression of: A+B = Q. Then we can define the operation of a 2-input logic OR gate as being: “If either A or B is true, then Q is true” 2-input Transistor OR Gate A simple 2-input logic OR gate can be constructed using RTL Resistor-transistor switches connected together as shown below with the inputs connected directly to the transistor bases. Either transistor must be saturated “ON” for an output at Q.
  • 45. 45 | P a g e desired logical function and is given a symbol whose shape represents the logical operation of the OR gate. Digital Logic “OR” Gate Types The 2-input Logic OR Gate Symbol Truth Table 2-input OR Gate B A Q 0 0 0 0 1 1 1 0 1 1 1 1 Boolean Expression Q = A+B Read as A OR B gives Q The 3-input Logic OR Gate Symbol Truth Table 3-input OR Gate C B A Q 0 0 0 0 0 0 1 1
  • 46. 46 | P a g e 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Boolean Expression Q = A+B+C Read as A OR B OR C gives Q Like the AND gate, the OR function can have any number of individual inputs. However, commercial available OR gates are available in 2, 3, or 4 inputs types. Additional inputs will require gates to be cascaded together for example. Multi-input OR Gate The Boolean Expression for this 6-input OR gate will therefore be: Q = (A+B)+(C+D)+(E+F)
  • 47. 47 | P a g e If the number of inputs required is an odd number of inputs any “unused” inputs can be held LOW by connecting them directly to ground using suitable “Pull-down” resistors. 4.6 Proteus Simulation
  • 48. 48 | P a g e Chapter 5 Cadence Implementations 5.1 About Cadence: Today Electronics devices are everywhere, in pockets, cars, homes, workplaces, everywhere. Smartphonees and mobile devices connect everyone, anywhere. These mobiles contain ‘apps’ which complete different complex tasks for the users. This newly connected, ‘app dependent’ world is built on the revolution of semiconductor and manufacturing. A single device might be built on billions of transistors. Systems-on- chips(SoCs) combine processors, memory, analog components, interface protocols and more. These type of complex calculations need huge powerful software for design, while meeting demands for performance, low power, and time to market. EDA (Electronic Design Automation) tools make it possible. EDA software and hardware enables everything from the design of individual transistors to the development of software before any hardware is built. Also, semiconductor intellectual property (IP) which provides pre-verified building blocks for memory controllers, specialized processors that are integrated into SoCs. Cadence is the leading provider of EDA and Semiconductor IP. Products of Cadence: Cadence's product offerings are targeted at various types of design and verification tasks which include:  Virtuoso Platform - Tools for designing full-custom integrated circuits, includes schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.  Encounter Platform - Tools for implementation of digital integrated circuits. This includes floorplanning, test, place and route and clock tree synthesis. Typically a digital design implementation starts from Verilog netlists from the synthesized design. Includes Nanoroute technology in the routing stage.  Incisive Platform - Tools for simulation and functional verification of RTL including Verilog, VHDL and SystemC based models. Includes formal verification, formal equivalence checking, hardware acceleration, and emulation.  Palladium series - Accelerators and emulators for hardware and software co- verification and system-level verification.
  • 49. 49 | P a g e  Design IP - Cadence provides design IP targeting areas including memory (DRAM), covering DDR1, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and Wide I/O; storage (non-volatile memory), covering NVM Express and NAND Flash controller and PHY; and high-performance interface protocols such as PCI Express Gen3, 40/100G Ethernet, and USB 2 and USB 3.  Verification IP (VIP) - Cadence provides the broadest set of commercial VIP available with over 30 protocols in its VIP Portfolio. They include AMBA, PCI Express, USB, SATA,OCP, SAS, MIPI and many others. Cadence VIP also provides the unique Compliance Management System (CMS) to automate protocol compliance verification.  Integration Optimized IP (Design IP) - Cadence offers Vertically Integrated IP, inclusive of Digital Controller, Serdes Layer, and Device Driver. Protocols supported include USB, DDR, PCI-Express, 10G-40G Ethernet, and On Chip Bus Fabric.  Allegro Platform - Tools for co-design of integrated circuits, packages, and PCBs.  OrCAD/PSpice - Tools for smaller design teams and individual PCB designers.[14]  Sigrity technologies - Tools for signal and power verification for system-level signoff verification and interface compliance.[15]  Since the acquisition of Tensilica in 2013 in the business of semiconductor intellectual property core In addition to EDA software, Cadence provides contracted methodology and design services as well as silicon design IP, and has a program aimed at making it easier for other EDA software to interoperate with the company's tools. 5.2 Cadence Library: Generic Process Design Kit(GPDK) known as cadence library. There are 45nm Process, 90nm Process, 180nm Process etc. 5.3 About Virtouso tool: Virtuoso creates Analog Design Environment for advanced design and simulation. It gives access to a new parasitic estimation and comparison flow and optimization algorithms that help to center designs better for yield improvement and advanced matching and sensitivity analyses. By supporting extensive exploration of multiple designs against their objective specifications, Virtuoso Analog Design Environment sets the standard in fast and accurate design verification. Features/Benefits Reduced learning curve with a simulator-independent environment Maximum efficiency in the script-driven mode
  • 50. 50 | P a g e Accelerated debug process using a variety of built-in analog analysis tools Facilitated design correction via easy comparison of pre- and post-parasitic extracted designs Quick detection of circuit problems via a clear visualization cockpit. 5.4 About Virtuoso Layout Suite: Cadence Virtuoso Layout Suite supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels. The enhanced Virtuoso Layout Suite offers accelerated performance and productivity from advanced full custom polygon editing through more flexible schematic and constraint-driven full custom layout, to full custom layout automation. Seamlessly integrated with the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, the Virtuoso Layout Suite enables the creation of differentiated custom silicon that is both fast and silicon accurate. Features/Benefits  New patented graphics-rendering engine provides from 10X to 100X accelerated zoom, fit, pan, drag, and redraw performance on large layouts  New Virtuoso Layout Suite XL connectivity extractor technology accelerates trace net, probe net, and mark net performance from 10X to 50X on large layouts  Patented multi-user Express PCell capability continues to boost design opening performance from 10X to 20X whenever users require PCell evaluation  New patented stream in engine provides accelerated performance from 2X to 20X  Virtuoso Space-Based Routing technology automatically enforces process and design rules during interactive and assisted wire and bus editing  Virtuoso module generators (ModGens) add a new interactive pattern manipulation flow, making real-time customization of a high-precision structured layout very visual and simple  Virtuoso Space-Based Routing technology at chip levels can deliver high-quality constraints and specialty routing to close thousands of nets in minutes, and new structured device-level routing capabilities that can enhance routing productivity by as much as 50%  The Virtuoso platform is backed by the largest number of process design kits (PDKs) available from the world’s leading foundries, for process nodes everywhere from mature 0.6µm to advanced 7nm process node.
  • 51. 51 | P a g e 5.5 Scale-Calculations: Scale calculation refers to the number of transistors/MOSFETS in a design. Typical scale division are: Scale No of transistors small-scale integration (SSI) 2-100 medium-scale integration (MSI) 100–500 large-scale integration (LSI) 500–20,000 very-large-scale integration (VLSI) 20,000–1,000,000 ultra-large scale integration (ULSI) >1,000,000 5.6 Analog Design Parameters: 5.6.1 The MOSFET The MOSFET – Metal Oxide FET Or, Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying channel and is therefore called an Insulated Gate Field Effect Transistor or IGFET. The most common type of insulated gate FET which is used in many different types of electronic circuits is called the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main semiconductor n-channel or p-channel by a very thin layer of insulating material usually silicon dioxide, commonly known as glass.
  • 52. 52 | P a g e This ultra thin insulated metal gate electrode can be thought of as one plate of a capacitor. The isolation of the controlling Gate makes the input resistance of the MOSFET extremely high way up in the Mega-ohms ( MΩ ) region thereby making it almost infinite. As the Gate terminal is isolated from the main current carrying channel “NO current flows into the gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the current flowing through the main channel between the Drain and Source is proportional to the input voltage. Also like the JFET, the MOSFETs very high input resistance can easily accumulate large amounts of static charge resulting in the MOSFET becoming easily damaged unless carefully handled or protected. MOSFETs are three terminal devices with a Gate, Drain and Source and both P-channel (PMOS) and N-channel (NMOS) MOSFETs are available. The main difference this time is that MOSFETs are available in two basic forms:  Depletion Type – the transistor requires the Gate-Source voltage, (VGS ) to switch the device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch.  Enhancement Type – the transistor requires a Gate-Source voltage, (VGS ) to switch the device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open” switch. The symbols and basic construction for both configurations of MOSFETs are shown below MOSFET
  • 53. 53 | P a g e The four MOSFET symbols above show an additional terminal called the Substrate and is not normally used as either an input or an output connection but instead it is used for grounding the substrate. It connects to the main semi conductive channel through a diode junction to the body or metal tab of the MOSFET. Usually in discrete type MOSFETs, this substrate lead is connected internally to the source terminal. When this is the case, as in enhancement type it is omitted from the symbol for clarification. The line between the drain and source connections represents the semi conductive channel. If this is a solid unbroken line then this represents a “Depletion” (normally-ON) type MOSFET as drain current can flow with zero gate potential. If the channel line is shown dotted or broken it is an “Enhancement” (normally-OFF) type MOSFET as zero drain current flows with zero gate potential. The direction of the arrow indicates whether the conductive channel is a p-type or an n-type semiconductor device. Basic MOSFET Structure and Symbol The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction FET. Both the Depletion and Enhancement type MOSFETs use an electrical field produced by a gate voltage to alter the flow of charge carriers, electrons for n-channel or holes for P-channel, through the semi conductive drain-source channel. The gate electrode is placed on top of a very thin insulating layer and there are a pair of small n-type regions just under the drain and source electrodes. The gate of a junction field effect transistor, JFET must be biased in such a way as to reverse- bias the pn-junction. With a insulated gate MOSFET device no such limitations apply so it is possible to bias the gate of a MOSFET in either polarity, positive (+ve) or negative (-ve).
  • 54. 54 | P a g e This makes the MOSFET device especially valuable as electronic switches or to make logic gates because with no bias they are normally non-conducting and this high gate input resistance means that very little or no control current is needed as MOSFETs are voltage controlled devices. Both the p-channel and the n-channel MOSFETs are available in two basic forms, the Enhancement type and the Depletion type. Depletion-mode MOSFET The Depletion-mode MOSFET, which is less common than the enhancement mode types is normally switched “ON” (conducting) without the application of a gate bias voltage. That is the channel conducts when VGS = 0 making it a “normally-closed” device. The circuit symbol shown above for a depletion MOS transistor uses a solid channel line to signify a normally closed conductive channel. For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will deplete (hence its name) the conductive channel of its free electrons switching the transistor “OFF”. Likewise for a p-channel depletion MOS transistor a positive gate-source voltage, +VGS will deplete the channel of its free holes turning it “OFF”. In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and more current. While a -VGS means less electrons and less current. The opposite is also true for the p-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed” switch. Depletion-mode N-Channel MOSFET and circuit Symbols
  • 55. 55 | P a g e The depletion-mode MOSFET is constructed in a similar way to their JFET transistor counterparts were the drain-source channel is inherently conductive with the electrons and holes already present within the n-type or p-type channel. This doping of the channel produces a conducting path of low resistance between the Drain and Source with zero Gate bias. Enhancement-mode MOSFET The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the depletion-mode type. Here the conducting channel is lightly doped or even undoped making it non-conductive. This results in the device being normally “OFF” (non-conducting) when the gate bias voltage, VGS is equal to zero. The circuit symbol shown above for an enhancement MOS transistor uses a broken channel line to signify a normally open non-conducting channel. For the n-channel enhancement MOS transistor a drain current will only flow when a gate voltage (VGS ) is applied to the gate terminal greater than the threshold voltage ( VTH ) level in which conductance takes place making it a trans conductance device. The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts more electrons towards the oxide layer around the gate thereby increasing or enhancing (hence its name) the thickness of the channel allowing more current to flow. This is why this kind of transistor is called an enhancement mode device as the application of a gate voltage enhances the channel. Increasing this positive gate voltage will cause the channel resistance to decrease further causing an increase in the drain current, ID through the channel. In other words, for an n-channel enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS turns the transistor “OFF”. Then, the enhancement-mode MOSFET is equivalent to a “normally-open” switch. The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the device is “OFF” and the channel is open. The application of a negative (-ve) gate voltage to the p-type eMOSFET enhances the channels conductivity turning it “ON”. Then for an p-channel enhancement mode MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the transistor “ON”.
  • 56. 56 | P a g e Enhancement-mode N-Channel MOSFET and Circuit Symbols Enhancement- mode MOSFETs make excellent electronics switches due to their low “ON” resistance and extremely high “OFF” resistance as well as their infinitely high input resistance due to their isolated gate. Enhancement-mode MOSFETs are used in integrated circuits to produce CMOS type Logic Gates and power switching circuits in the form of as PMOS (P-channel) and NMOS (N-channel) gates. CMOS actually stands for Complementary MOS meaning that the logic device has both PMOS and NMOS within its design. So, the summary of MOSFET can be showed by this chart:
  • 57. 57 | P a g e 5.6.2 Why use MOSFET over BJT as a switch? MOSFET BJT Voltage Driven Current Driven Works in High and low frequencies Works in lower frequencies than MOSFET Swithes faster Swithes lower than MOSFET Wastes no current on gate Wastes current on base More energy efficient Less energy efficient Suitable for driving high power Suitable for driving low powr More expensive Less expensive If both of the characteristics are needed somewhere, we can use IGBT (insulated-gate bipolar transistor ) IGBT comparison table: 5.7 Regions of MOSFET operation:
  • 58. 58 | P a g e VGS = voltage between gate to source VDS = voltage between drain to source ID = current flowing through drain. VT = Threshold voltage(Minimum voltage to switch ON a MOSFET) If we give a gate voltage to MOSFET gate, according to the voltage, the MOSFET switches. MOSFET Regions of Operation • There are three regions of operation in the MOSFET – When VGS < VT, no conductive channel is present and ID = 0, the cutoff region – When VGS < VT and VDS < VDS, sat, the device is in the triode region of operation. Increasing VDS increases the lateral field in the channel, and hence the current. Increasing VGS increases the transverse field and hence the inversion layer density, which also increases the current – If VGS < VT and VDS > VDS, sat, the device is in the saturation region of operation. Since the drain end channel density has become small, the current is much less dependent on VDS , but is still dependent on VGS, since increased VGS still increases the inversion layer density MOSFET ID-VDS Characteristic For VGS < VT , ID = 0 . As VDS increases at a fixed VGS , ID increases in the triode region due to the increased lateral field, but at a decreasing rate since the inversion layer density is decreasing. Once pinchoff is reached, further VDS increases only increase ID due to the formation of the high field region. MOSFET ID-VGS Characteristic As ID is increased at fixed VDS, no current flows until the inversion layer is established. For VGS slightly above threshold, the device is in saturation since there is little inversion layer density (the drain end is pinched off) As VGS increases, a point is reached where the drain end is no longer pinched off, and the device is in the triode region. A larger VDS value postpones the point of transition to triode.
  • 59. 59 | P a g e The device starts in triode, and moves into saturation at higher VDS. MOSFET equations:
  • 60. 60 | P a g e 5.8 CMOS Basics: Complementary CMOS  Comlementary CMOS Logic Gates:  nMOS pull-down network „  pMOS pull-up network „  Static CMOS
  • 61. 61 | P a g e  Complementary CMOS gates always produce 1 or 0  Pull-up network is complement (dual) of pull-down network Building CMOS Gates (n-side) CMOS is inherently inverting. „  Gates with expression of the form F = 𝐸𝑋𝑃𝑅𝐸𝑆𝑆𝐼𝑂𝑁 are easier to build.  For making the n-side (pull-down network) use the un-inverted expression.  For e.g.: Implement „F = ( 𝐴. 𝐵 + 𝐶. 𝐷 )  For n-side use „F= ((A.B)+(C.D))  AND expressions are implemented using series connection of n transistors „  OR expressions are implemented using parallel connection of n transistors. Building CMOS Gates (p-side)  For making the p-side (pull-up network) invert the expression used for n-side. „  For e.g.: Implement „F = ( 𝐴. 𝐵 + 𝐶. 𝐷 )  For n-side use F= ((A.B)+(C.D))  For p-side invert above expression: „F = (𝐴 + 𝐵).(𝐶 + 𝐷)  AND expressions are implemented using series connection of p transistors „  OR expressions are implemented using parallel connection of p transistors
  • 62. 62 | P a g e Building CMOS Gates (Final CMOS gate) Combine the n-side (pull-down) and p-side (pull-up) to make the final gate. F = ( 𝐴. 𝐵 + 𝐶. 𝐷 )
  • 63. 63 | P a g e 5.9 Differential Amplifier MOSFET is the most widely used transistor in both digital and analog circuits, and it is the backbone of modern electronics. One of the most common uses of the MOSFET in analog circuits is the construction of differential amplifiers. The latter are used as input stages in op- amps, video amplifiers, high-speed comparators, and many other analog-based circuits. MOSFET differential amplifiers are used in integrated circuits, such as operational amplifiers, they provide high input impedance for the input terminals. A properly designed differential amplifier with its current-mirror biasing stages is made from matched-pair devices to minimize imbalances from one side of the differential amplifier to the other. Differential Amplifier: An electronic amplifier amplifies the difference between two input voltages but suppresses any voltage common to the two inputs. It is an analog circuit with two inputs Vin+ and Vin- and one output Vout in which the output is ideally proportional to the difference between the two voltages. Vout = A(Vin+ - Vin-) where A is the gain of the amplifier. In the figure , V+ = Vin+ V- = Vin- BACKGROUND : The general topology of a differential amplifier is shown below. Two active devices are connected to a positive voltage supply via passive series elements. The transistors must be a matched pair (i.e., two matched MOSFETs or two matched BJTs). The "pull up" loads are similarly matched to each other. The lower terminals of the active devices are connected together, and a dc current source pulls current down toward the negative voltage bus to effect the bias. The controlling input ports of the devices are connected to input signals.
  • 64. 64 | P a g e If the input signals are designated v1 and v2 , they can be decomposed into two linear combinations, one called the differential mode, and the other the common mode. The differential mode is defined by the following equation: vidm = v1-v2 Similarly, the common mode, equal to the average value of the signals, is defined by: vicm = v1+v2 2 These definitions allow the actual input signals v1 and v2 to be expressed as linear combinations of their differential and common modes: v1 = vicm + vidm 2 = v1+v2 2 + v1−v2 2 = v1 v2 = vicm - vidm 2 = v1+v2 2 - v1−v2 2 = v2 because the small-signal model of the amplifier is linear, its total response will be equal to the superposition of its responses to, respectively, the differential and common modes of the input signals. Current Mirror MOFETS: The common-mode gain of the differential amplifier will be small (desirable) if the small-signal Norton, resistance rn of the biasing current source is large. The biasing current source is not a naturally occurring element, but must be synthesized from other transistors. In most situations, the designer will choose some form of current mirror to produce the equivalent current source. The circuit on the left, shown below, is equivalent in all respects to the symbolic current-source component on the right. In the current mirror circuit shown on the left, the reference current is set by the resistor. The voltage across the latter is given by the voltage drop across because the two MOSFETs are matched, and have precisely the same gate-source and threshold voltages (vGSA = vGSB), their drain currents will be equal. Thus, the current I0 becomes a replica, or "mirror image" of the reference current. As long as QB remains in its constant current region, then this replication will take place. Note that QA automatically operates in its constant current region, because it's gate is connected to its drain. The Norton resistance rn the current source will be equal to the output resistance ro of QB, as determined by the upward slope of that transistor's voltage-current characteristic.
  • 65. 65 | P a g e Current Biasing MOSFETS: In an Differential amplifier, we use current biasing MOSFET’s to keep all the FET’s in saturation region. To keep this MOSFET in saturation region we need to current mirror it with another MOSFET. If the biasing MOSFET is PMOS, then it’s mirror will also be PMOS. If the biasing MOSFET is NMOS, then it’s mirror will also be NMOS. The mirror PMOS’s source will be connected to voltage supply. The mirror NMOS’s drain will be connected to voltage supply. The figure shows a single stage differential amplifier. V1 and V2 are differential inputs and M5 and M6 are mirroring MOSFETS. M1 here is the current biasing MOSFETS because the current flowing through M1 is the summation of the current of BRANCH 1 and BRANCH 2. The mirror of M1 is M2 which ones drain is connected to M7 which is acting as a current source (idc).
  • 66. 66 | P a g e ICMR+ and ICMR- : Input common-mode range (ICMR) is the range of common-mode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Typically, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region. ICMR+ > All MOSFET saturation > ICMR- Common mode rejection ratio (CMRR) CMRR is a measure of how well the differential amplifier rejects the common-mode input voltage in favor of the differential-input voltage. CMRR = Differe ntial mode voltage gain Common mode voltage gain The differential-mode input voltage = v1 - v2. The common-mode input voltage = v1+ v2 2 Output offset voltage VOS(out) The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together. Input offset voltage VOS(in) The input offset voltage is equal to the output offset voltage divided by the differential voltage gain. VOS(in) = 𝑉𝑂𝑆(𝑜𝑢𝑡 ) 𝐴𝑣 5.10 Slew Rate Slew rate is the maximum voltage change per unit time in a node of a circuit, due to limited current sink or source. Explanation: The figure shows a differential amplifier with a load capacitor Cload. Input V+ and V- and supply voltage Vdd and ground. Now,  V+ and V- are inverse sinewave.  If we increase V+, V- decreases.
  • 67. 67 | P a g e  If we increase V-, V+ decreases.  Step 1 :  Increase V- , so at a point V+ will be ≈ 0.  No current will flow through branch 1.  All current will flow through branch 2.  Cload will be charged.  Step 2:  Increase V+ , so at a point V- will be ≈ 0.  No current will flow through branch 2.  All current will flow through branch 1.  Cload will be discharged. The rate of charge of charging or discharging of capacitor is typically known as Slew rate. Itotal = Cload x Slew Rate = Cload x c 𝑑𝑣𝑐 𝑑𝑡 5.11 Common source, Common Gate, Common Drain amplifiers:
  • 68. 68 | P a g e Common Source, Common Gate, Common Drain amplifier: Common source: Typically known as Voltage amplifier, It has higher input resistance and lower gain than CE amplifier. The voltage gain is given by the equation Av = gmRd. Rd is the resistance between drain to supply voltage. Characteristics (small signal): Common Drain: Used as Voltage buffer, also used for transform impedances. The voltage gain is given by the equation Small Signal Characteristics: 1 m s v m s g R A g R  
  • 69. 69 | P a g e Common Gate: Typically used as a current buffer or voltage amplifier. The analogous bipolar junction transistor circuit is the common-base amplifier. Characteristics: 5.12 Designing in Cadence: From the previous chapter, we got the design of LVD, HVD. To design those parts in Cadence, we need to design: 1. And Gate & And gate Layout 2. Or Gate & Or gate Layout 3. Inverter & Inverter layout 4. Comparator & Comparator Layout AND GATE: Calculations: Pull Down Part: 120 100 + 120 100 = 120 200 (as though the FET’s are in series, their length will be added) = 240 100 (each) Pull up Part: = 3 x 240 100 = 720 100 = 360 100 (each)
  • 70. 70 | P a g e Logic: F = A.B = 𝐴. 𝐵 = 𝐴 + 𝐵 = 𝐴 + 𝐵 (inverter) = A.B Schematic
  • 71. 71 | P a g e Layout: Height = 3μ Length = integer of 0.3μ Height of Vdd and Vss = 0.53μ OR GATE: Calculations: Pull Down Part: 120 100 + 120 100 = 240 100 (as though the FET’s are in parallel, their width will be added) =120/100 (each) Pull up part = 3 x 240 100 = 720 100 = 360 100 (each)
  • 72. 72 | P a g e Logic: F = A + B = 𝐴 + 𝐵 = 𝐴 . 𝐵 = 𝐴 . 𝐵 (inverter) = A + B Schematic:
  • 73. 73 | P a g e Layout: Height = 3μ Length = integer of 0.3μ Height of Vdd and Vss = 0.53μ
  • 74. 74 | P a g e 5.13 Comparator: COMPARATOR WORKING PRINCIPLE: When  Variable i/p is at V1  VREF is at V2  If V1>V2, then o/p= +Vcc else o/p= -Vcc
  • 75. 75 | P a g e Challenges to design comparator:  Remove feedback of non-inverting OPAMP and turn it into comparator.  Meet of some conditions.  Keep gain at least Av = ~10,000  Suitable for this design. Conditions:  Slew Rate = 10v/μs  VDD = 1.8 V  VSS = 0 V  o/p swing = 1.8 V  ICMR+ = 1.6 V  ICMR- = 1.4 V  Vout = 0 < 1.8 Comparator Block Diagram:
  • 76. 76 | P a g e 5.14 Calculations: Cload = 2pF ID7 = CL x SR = (2 x 10^-12)(10^6) = 20 μA VDS7(SAT) = Vo(min) – Vss = 0 – 0 = 0 ≈ 0.5v VDS7(SAT) = 2𝐼𝐷𝑆7 𝛽7 = 2𝐼𝐷𝑆7 𝐾𝑁 𝑊 𝐿 7  𝑊 𝐿 7 = { 2𝐼𝐷𝑆7 𝐾𝑁( 𝑉𝐷𝑆(𝑆𝐴𝑇 2) }^2  = { 2(20𝑥10−6) 344.16𝜇( 0.5 2) } ^2 ( βN = 413μ and initial w/L= 1.2)   = 0.46 Now, VDS6(SAT) ≈ 0.5  𝑊 𝐿 6 = { 2𝐼𝐷𝑆6 𝐾𝑃( 𝑉𝐷𝑆(𝑆𝐴𝑇 2) }^2 = { 2(20𝑥10−6) 264𝜇( 0.5 2) } ^2 ( βP = 366μ and initial w/L= 1.2)  = 0.6 Considering initial ( 𝑊 𝐿)4 =1.2 to determine current ISD4 which is mirror with M6. ISD4 = ( 𝑊 𝐿)4 ( 𝑊 𝐿)6 ISD6 = 1.2 0.6 (20μ) = 40μ Considering initial ( 𝑊 𝐿)5 = 1.2 to determine current ISD4 which is mirror with M7. ISD5 = ( 𝑊 𝐿)5 ( 𝑊 𝐿)6 ISD6 = 1.2 0.4 (20μ) = 60μ ISD4 = 𝐼𝐷𝑆5 2 = 30μ = ISD3
  • 77. 77 | P a g e IDS2 = IDS1 = 𝐼𝐷𝑆5 2 = 30μType equation here. ( 𝑊 𝐿)4 = 𝐼𝑆𝐷4 𝐼𝑆𝐷6 ( 𝑊 𝐿)6 = 30𝜇 20𝜇 (0.6) = 0.72 𝑁𝑂𝑊 𝑊 𝐿 5 = 2𝐼𝐷𝑆5 𝐾𝑁 𝑉𝐷𝑆 𝑆𝐴𝑇 ^2 VDS5(SAT) = VGI(MIN)-VSS- 2𝐼𝐷𝑆1 𝐾𝑁( 𝑊 𝐿)1 - VT1 = 1.4 - 0 - 2(30𝜇) 344.16𝜇(1.2) - 0.7 = 0.56 V So, 𝑊 𝐿 5 = 2(60𝜇) 344.16𝜇 0.56 ^2 = 1.22 VGI(MAX) = VDD - 2𝐼𝑆𝐷3 𝐾𝑃( 𝑊 𝐿)3 - VT3 + VT1  ( 𝑊 𝐿)3 = 2𝐼𝑆𝐷3 𝐾𝑃 𝑉𝐷𝐷−𝑉𝐺1 𝑀𝐴𝑋 −𝑉𝑇3+𝑉𝑇1 2  = 2(30𝜇) 264𝜇 1.8−1.6−0.7+0.7 2  = 5.68 Now, M9 working as a current source, (𝑊 𝐿)3 = 1 After ADE L simulation, to get perfect (W/L) ratio for all MOSFETS: M1 M2 M3 M4 M5 M6 M7 M8 M9 ( 𝑊 𝐿) 0.81 0.81 1.09 1.09 0.81 9 3.35 3.35 1 Calculations of Second Stage Gain : Av2 = 2𝐾𝑃𝐼𝑆𝐷6( 𝑊 𝐿)6 𝐼𝑆𝐷6(𝜆𝑃+𝜆𝑁) = 2 264𝜇 (20𝜇)(9) (20𝜇)(0.005+0.005) ≈ 100 So, the first stage gain will be Av1Av2=10,000 So, Av2= 100. Schematic of comparator:
  • 78. 78 | P a g e Schematic(Cellview):
  • 79. 79 | P a g e Output: Layout: For layout, we eliminated the capacitor because of design. And also, the design has cap for itself without the load capacitor.
  • 80. 80 | P a g e 5.15 HVD(High Voltage Disconnect): The HVD part is shown below:
  • 81. 81 | P a g e Layout of the logic part: Layout of whole part:
  • 82. 82 | P a g e 5.16 LVD (Low Voltage Disconnect) Layout:
  • 83. 83 | P a g e Conclusion: This study presents whole description of component like solar panel, solar charge controller. Proteus simulation if whole system is shown here. As, our aim was to design a solar charge controller using analog components, we explained our calculations and simulations in cadence analog designing. We showed the HVD and LVD parts both in Cadence and Proteus, We connected them and showed that the whole design works. At last, we completed the Layout for each design and connected them. This design is energy and area efficient. It consumes less power and can be implemented in mot designs. This system can be modified by further research and could be used in modern technologies.
  • 84. 84 | P a g e References: https://en.wikipedia.org/wiki/ http://webpages.eng.wayne.edu/ http://www.csee.umbc.edu/ http://electronics.stackexchange.com/ https://inst.eecs.berkeley.edu/ http://ecee.colorado.edu/ https://www.quora.com/ http://www.electronics-tutorials.ws/ https://www.youtube.com/ http://ic.sjtu.edu.cn/ic/wp-content/uploads/sites/10/2013/04/CMOS-VLSI- design.pdf Bahzad Razavi Book : Design of Analog CMOS integrated circuit.